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ae7ba525a5
Add device-tree description for the EEPROM devices on Armada 388 SOM rev 2.1. Another EEPROM is now on Clearfog Pro carrier rev 2.2, and Clearfog Base rev 1.3. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
382 lines
8.9 KiB
Plaintext
382 lines
8.9 KiB
Plaintext
/*
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* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-388.dtsi"
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#include "armada-38x-solidrun-microsom.dtsi"
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/ {
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model = "SolidRun Clearfog A1";
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compatible = "solidrun,clearfog-a1", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet1 = ð0;
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ethernet2 = ð1;
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ethernet3 = ð2;
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spi1 = &spi1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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soc {
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internal-regs {
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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* twice in u-boot.
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*/
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status = "okay";
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};
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sata@a8000 {
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/* pinctrl? */
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status = "okay";
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};
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sata@e0000 {
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/* pinctrl? */
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status = "okay";
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};
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sdhci@d8000 {
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bus-width = <4>;
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cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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pinctrl-0 = <µsom_sdhci_pins
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&clearfog_sdhci_cd_pins>;
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pinctrl-names = "default";
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status = "okay";
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vmmc = <®_3p3v>;
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wp-inverted;
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};
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serial@12100 {
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/* mikrobus uart */
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pinctrl-0 = <&mikro_uart_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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usb3@f8000 {
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/* CON7, USB-A port on back of device */
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status = "okay";
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};
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};
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pcie {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* the mini-PCIe connectors on the board.
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*/
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pcie@2,0 {
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/* Port 1, Lane 0. CONN3, nearest power. */
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reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0. CONN2, nearest CPU. */
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reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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};
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&w25q32 {
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status = "okay";
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};
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ð1 {
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managed = "in-band-status";
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phy-mode = "sgmii";
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status = "okay";
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};
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ð2 {
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phy-mode = "sgmii";
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* PCA9655 GPIO expander, up to 1MHz clock.
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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expander0: gpio-expander@20 {
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/*
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* This is how it should be:
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* compatible = "onnn,pca9655",
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* "nxp,pca9555";
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* but you can't do this because of
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* the way I2C works.
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*/
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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pcie1_0_clkreq {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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pcie1_0_w_disable {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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usb3_ilimit {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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input;
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line-name = "usb3-current-limit";
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};
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usb3_power {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb3-power";
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};
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m2_devslp {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "m.2 devslp";
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};
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};
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mikrobus_adc: mcp3021@4c {
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compatible = "microchip,mcp3021";
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reg = <0x4c>;
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};
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eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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};
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&i2c1 {
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/*
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* Routed to SFP, mikrobus, and PCIe.
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* SFP limits this to 100kHz, and requires
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* an AT24C01A/02/04 with address pins tied
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* low, which takes addresses 0x50 and 0x51.
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* Mikrobus doesn't specify beyond an I2C
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* bus being present.
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* PCIe uses ARP to assign addresses, or
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* 0x63-0x64.
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*/
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clock-frequency = <100000>;
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pinctrl-0 = <&clearfog_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pinctrl {
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clearfog_i2c1_pins: i2c1-pins {
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/* SFP, PCIe, mSATA, mikrobus */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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mikro_pins: mikro-pins {
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/* int: mpp22 rst: mpp29 */
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marvell,pins = "mpp22", "mpp29";
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marvell,function = "gpio";
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};
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mikro_spi_pins: mikro-spi-pins {
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marvell,pins = "mpp43";
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marvell,function = "spi1";
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};
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mikro_uart_pins: mikro-uart-pins {
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marvell,pins = "mpp24", "mpp25";
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marvell,function = "ua1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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&spi1 {
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/*
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* Add SPI CS pins for clearfog:
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* CS0: W25Q32
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* CS1:
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* CS2: mikrobus
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*/
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pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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/*
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+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
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MPP18: gpio ? (pca9655 int?)
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MPP19: gpio ? (clkreq?)
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MPP20: gpio ? (sd0 detect)
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MPP21: sd0:cmd x sd0
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MPP22: gpio x mikro int
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MPP23: gpio x switch irq
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+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
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MPP24: ua1:rxd x mikro rx
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MPP25: ua1:txd x mikro tx
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MPP26: i2c1:sck x mikro sck
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MPP27: i2c1:sda x mikro sda
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MPP28: sd0:clk x sd0
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MPP29: gpio x mikro rst
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MPP30: ge1:txd2 ? (config)
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MPP31: ge1:txd3 ? (config)
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+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
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MPP32: ge1:txctl ? (unused)
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MPP33: gpio ? (pic_com0)
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MPP34: gpio x rear button (pic_com1)
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MPP35: gpio ? (pic_com2)
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MPP36: gpio ? (unused)
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MPP37: sd0:d3 x sd0
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MPP38: sd0:d0 x sd0
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MPP39: sd0:d1 x sd0
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+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
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MPP40: sd0:d2 x sd0
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MPP41: gpio x switch reset
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MPP42: gpio ? sw1-1
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MPP43: spi1:cs2 x mikro cs
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MPP44: sata3:prsnt ? (unused)
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MPP45: ref:clk_out0 ?
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MPP46: ref:clk_out1 x switch clk
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MPP47: 4 ? (unused)
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+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
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MPP48: tdm:pclk
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MPP49: tdm:fsync
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MPP50: tdm:drx
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MPP51: tdm:dtx
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MPP52: tdm:int
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MPP53: tdm:rst
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MPP54: gpio ? (pwm)
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MPP55: spi1:cs1 x slic
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+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
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MPP56: spi1:mosi x mikro mosi
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MPP57: spi1:sck x mikro sck
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MPP58: spi1:miso x mikro miso
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MPP59: spi1:cs0 x w25q32
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*/
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