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c8b98482d8
Add both DRAM banks memory information and the corresponding MMU page table mappings. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
48 lines
1006 B
Plaintext
48 lines
1006 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Broadcom
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*/
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/dts-v1/;
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#include <dt-bindings/memory/bcm-ns3-mc.h>
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/*
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* Single mem reserve region which includes the following:
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* Components name Start Addr Size
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* ------------------------------------------------
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* GIC LPI tables 0x8ad7_0000 0x0009_0000
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* Nitro FW 0x8ae0_0000 0x0020_0000
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* Nitro Crash dump 0x8b00_0000 0x0200_0000
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* OPTEE OS 0x8d00_0000 0x0200_0000
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* BL31 services 0x8f00_0000 0x0010_0000
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* Tmon 0x8f10_0000 0x0000_1000
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* LPM/reserved 0x8f10_1000 0x0000_1000
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* ATF to Bl33 info 0x8f10_2000 0x0000_1000
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* ATF error logs 0x8f10_3000 0x0001_0000
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* Error log parser 0x8f11_3000 0x0010_0000
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*/
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/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END;
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/* CRMU page tables */
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/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE;
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#include "ns3.dtsi"
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/ {
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model = "NS3 model";
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aliases {
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serial0 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart1 {
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status = "okay";
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};
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