mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 03:58:17 +00:00
26671aabcc
Fixed the following DTC build warning (reproducible with W=1) arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ohci@00400000: unit name should not have leading 0s arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ehci@00500000: unit name should not have leading 0s Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com>
787 lines
16 KiB
Plaintext
787 lines
16 KiB
Plaintext
#include "skeleton.dtsi"
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/ {
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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aliases {
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spi0 = &spi0;
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spi1 = &qspi0;
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spi2 = &qspi1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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usb1: ohci@400000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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clocks = <&utmi>, <&uhphs_clk>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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hlcdc: hlcdc@f0000000 {
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compatible = "atmel,at91sam9x5-hlcdc";
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reg = <0xf0000000 0x2000>;
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clocks = <&lcdc_clk>;
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status = "disabled";
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};
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pmc: pmc@f0014000 {
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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u-boot,dm-pre-reloc;
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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plla: pllack@0 {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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u-boot,dm-pre-reloc;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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audio_pll_frac: audiopll_fracck {
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compatible = "atmel,sama5d2-clk-audio-pll-frac";
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#clock-cells = <0>;
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clocks = <&main>;
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};
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audio_pll_pad: audiopll_padck {
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compatible = "atmel,sama5d2-clk-audio-pll-pad";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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audio_pll_pmc: audiopll_pmcck {
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compatible = "atmel,sama5d2-clk-audio-pll-pmc";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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clocks = <&main>;
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regmap-sfr = <&sfr>;
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u-boot,dm-pre-reloc;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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clocks = <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <124000000 166000000>;
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atmel,clk-divisors = <1 2 4 3>;
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u-boot,dm-pre-reloc;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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u-boot,dm-pre-reloc;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog@0 {
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#clock-cells = <0>;
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reg = <0>;
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};
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prog1: prog@1 {
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#clock-cells = <0>;
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reg = <1>;
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};
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prog2: prog@2 {
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#clock-cells = <0>;
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reg = <2>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck@2 {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck@3 {
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#clock-cells = <0>;
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reg = <3>;
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clocks = <&mck>;
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};
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uhpck: uhpck@6 {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck@7 {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0@8 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1@9 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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pck2: pck2@10 {
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#clock-cells = <0>;
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reg = <10>;
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clocks = <&prog2>;
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};
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iscck: iscck@18 {
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#clock-cells = <0>;
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reg = <18>;
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clocks = <&mck>;
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};
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};
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periph32ck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&h32ck>;
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u-boot,dm-pre-reloc;
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macb0_clk: macb0_clk@5 {
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#clock-cells = <0>;
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reg = <5>;
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atmel,clk-output-range = <0 83000000>;
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};
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tdes_clk: tdes_clk@11 {
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#clock-cells = <0>;
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reg = <11>;
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atmel,clk-output-range = <0 83000000>;
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};
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matrix1_clk: matrix1_clk@14 {
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#clock-cells = <0>;
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reg = <14>;
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};
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hsmc_clk: hsmc_clk@17 {
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#clock-cells = <0>;
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reg = <17>;
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};
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pioA_clk: pioA_clk@18 {
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#clock-cells = <0>;
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reg = <18>;
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atmel,clk-output-range = <0 83000000>;
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u-boot,dm-pre-reloc;
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};
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flx0_clk: flx0_clk@19 {
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#clock-cells = <0>;
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reg = <19>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx1_clk: flx1_clk@20 {
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#clock-cells = <0>;
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reg = <20>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx2_clk: flx2_clk@21 {
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#clock-cells = <0>;
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reg = <21>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx3_clk: flx3_clk@22 {
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#clock-cells = <0>;
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reg = <22>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx4_clk: flx4_clk@23 {
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#clock-cells = <0>;
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reg = <23>;
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atmel,clk-output-range = <0 83000000>;
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};
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uart0_clk: uart0_clk@24 {
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#clock-cells = <0>;
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reg = <24>;
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atmel,clk-output-range = <0 83000000>;
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u-boot,dm-pre-reloc;
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};
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uart1_clk: uart1_clk@25 {
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#clock-cells = <0>;
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reg = <25>;
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atmel,clk-output-range = <0 83000000>;
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u-boot,dm-pre-reloc;
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};
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uart2_clk: uart2_clk@26 {
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#clock-cells = <0>;
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reg = <26>;
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atmel,clk-output-range = <0 83000000>;
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u-boot,dm-pre-reloc;
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};
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uart3_clk: uart3_clk@27 {
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#clock-cells = <0>;
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reg = <27>;
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atmel,clk-output-range = <0 83000000>;
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};
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uart4_clk: uart4_clk@28 {
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#clock-cells = <0>;
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reg = <28>;
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atmel,clk-output-range = <0 83000000>;
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};
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twi0_clk: twi0_clk@29 {
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reg = <29>;
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#clock-cells = <0>;
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atmel,clk-output-range = <0 83000000>;
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};
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twi1_clk: twi1_clk@30 {
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#clock-cells = <0>;
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reg = <30>;
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atmel,clk-output-range = <0 83000000>;
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};
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spi0_clk: spi0_clk@33 {
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#clock-cells = <0>;
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reg = <33>;
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atmel,clk-output-range = <0 83000000>;
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u-boot,dm-pre-reloc;
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};
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spi1_clk: spi1_clk@34 {
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#clock-cells = <0>;
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reg = <34>;
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atmel,clk-output-range = <0 83000000>;
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};
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tcb0_clk: tcb0_clk@35 {
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#clock-cells = <0>;
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reg = <35>;
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atmel,clk-output-range = <0 83000000>;
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};
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tcb1_clk: tcb1_clk@36 {
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#clock-cells = <0>;
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reg = <36>;
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atmel,clk-output-range = <0 83000000>;
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};
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pwm_clk: pwm_clk@38 {
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#clock-cells = <0>;
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reg = <38>;
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atmel,clk-output-range = <0 83000000>;
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};
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adc_clk: adc_clk@40 {
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#clock-cells = <0>;
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reg = <40>;
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atmel,clk-output-range = <0 83000000>;
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};
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uhphs_clk: uhphs_clk@41 {
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#clock-cells = <0>;
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reg = <41>;
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atmel,clk-output-range = <0 83000000>;
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};
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udphs_clk: udphs_clk@42 {
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#clock-cells = <0>;
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reg = <42>;
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atmel,clk-output-range = <0 83000000>;
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};
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ssc0_clk: ssc0_clk@43 {
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#clock-cells = <0>;
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reg = <43>;
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atmel,clk-output-range = <0 83000000>;
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};
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ssc1_clk: ssc1_clk@44 {
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#clock-cells = <0>;
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reg = <44>;
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atmel,clk-output-range = <0 83000000>;
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};
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trng_clk: trng_clk@47 {
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#clock-cells = <0>;
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reg = <47>;
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atmel,clk-output-range = <0 83000000>;
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};
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pdmic_clk: pdmic_clk@48 {
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#clock-cells = <0>;
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reg = <48>;
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atmel,clk-output-range = <0 83000000>;
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};
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i2s0_clk: i2s0_clk@54 {
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#clock-cells = <0>;
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reg = <54>;
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atmel,clk-output-range = <0 83000000>;
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};
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i2s1_clk: i2s1_clk@55 {
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#clock-cells = <0>;
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reg = <55>;
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atmel,clk-output-range = <0 83000000>;
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};
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can0_clk: can0_clk@56 {
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#clock-cells = <0>;
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reg = <56>;
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atmel,clk-output-range = <0 83000000>;
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};
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can1_clk: can1_clk@57 {
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#clock-cells = <0>;
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reg = <57>;
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atmel,clk-output-range = <0 83000000>;
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};
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classd_clk: classd_clk@59 {
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#clock-cells = <0>;
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reg = <59>;
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atmel,clk-output-range = <0 83000000>;
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};
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};
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periph64ck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mck>;
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u-boot,dm-pre-reloc;
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dma0_clk: dma0_clk@6 {
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#clock-cells = <0>;
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reg = <6>;
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};
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dma1_clk: dma1_clk@7 {
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#clock-cells = <0>;
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reg = <7>;
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};
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aes_clk: aes_clk@9 {
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#clock-cells = <0>;
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reg = <9>;
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};
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aesb_clk: aesb_clk@10 {
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#clock-cells = <0>;
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reg = <10>;
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};
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sha_clk: sha_clk@12 {
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#clock-cells = <0>;
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reg = <12>;
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};
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mpddr_clk: mpddr_clk@13 {
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#clock-cells = <0>;
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reg = <13>;
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};
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matrix0_clk: matrix0_clk@15 {
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#clock-cells = <0>;
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reg = <15>;
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};
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sdmmc0_hclk: sdmmc0_hclk@31 {
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#clock-cells = <0>;
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reg = <31>;
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u-boot,dm-pre-reloc;
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};
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sdmmc1_hclk: sdmmc1_hclk@32 {
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#clock-cells = <0>;
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reg = <32>;
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u-boot,dm-pre-reloc;
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};
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lcdc_clk: lcdc_clk@45 {
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#clock-cells = <0>;
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reg = <45>;
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};
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isc_clk: isc_clk@46 {
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#clock-cells = <0>;
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reg = <46>;
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};
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qspi0_clk: qspi0_clk@52 {
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#clock-cells = <0>;
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reg = <52>;
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u-boot,dm-pre-reloc;
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};
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qspi1_clk: qspi1_clk@53 {
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#clock-cells = <0>;
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reg = <53>;
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u-boot,dm-pre-reloc;
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};
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};
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gck {
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compatible = "atmel,sama5d2-clk-generated";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&main>, <&plla>, <&utmi>, <&mck>;
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u-boot,dm-pre-reloc;
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sdmmc0_gclk: sdmmc0_gclk@31 {
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#clock-cells = <0>;
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reg = <31>;
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u-boot,dm-pre-reloc;
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};
|
|
|
|
sdmmc1_gclk: sdmmc1_gclk@32 {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
tcb0_gclk: tcb0_gclk@35 {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_gclk: tcb1_gclk@36 {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_gclk: pwm_gclk@38 {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_gclk: pdmic_gclk@48 {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
|
|
i2s0_gclk: i2s0_gclk@54 {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
i2s1_gclk: i2s1_gclk@55 {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
|
|
can0_gclk: can0_gclk@56 {
|
|
#clock-cells = <0>;
|
|
reg = <56>;
|
|
atmel,clk-output-range = <0 80000000>;
|
|
};
|
|
|
|
can1_gclk: can1_gclk@57 {
|
|
#clock-cells = <0>;
|
|
reg = <57>;
|
|
atmel,clk-output-range = <0 80000000>;
|
|
};
|
|
|
|
classd_gclk: classd_gclk@59 {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 100000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qspi0: spi@f0020000 {
|
|
compatible = "atmel,sama5d2-qspi";
|
|
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&qspi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi1: spi@f0024000 {
|
|
compatible = "atmel,sama5d2-qspi";
|
|
reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&qspi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "cdns,macb";
|
|
reg = <0xf8008000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
clocks = <&uart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
shdwc@f8048010 {
|
|
compatible = "atmel,sama5d2-shdwc";
|
|
reg = <0xf8048010 0x10>;
|
|
clocks = <&clk32k>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,wakeup-rtc-timer;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
watchdog@f8048040 {
|
|
compatible = "atmel,sama5d4-wdt";
|
|
reg = <0xf8048040 0x10>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfr: sfr@f8030000 {
|
|
compatible = "atmel,sama5d2-sfr", "syscon";
|
|
reg = <0xf8030000 0x98>;
|
|
};
|
|
|
|
sckc@f8048050 {
|
|
compatible = "atmel,at91sam9x5-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
slow_rc_osc: slow_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-accuracy = <250000000>;
|
|
atmel,startup-time-usec = <75>;
|
|
};
|
|
|
|
slow_osc: slow_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_xtal>;
|
|
atmel,startup-time-usec = <1200000>;
|
|
};
|
|
|
|
clk32k: slowck {
|
|
compatible = "atmel,at91sam9x5-clk-slow";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_rc_osc &slow_osc>;
|
|
};
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
clocks = <&uart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
clocks = <&uart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: gpio@fc038000 {
|
|
compatible = "atmel,sama5d2-gpio";
|
|
reg = <0xfc038000 0x600>;
|
|
clocks = <&pioA_clk>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pinctrl {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
onewire_tm: onewire {
|
|
compatible = "w1-gpio";
|
|
status = "disabled";
|
|
};
|
|
};
|