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f132c4967e
This patchset has following changes: - introduce stm32h750.dtsi to support stm32h750 value line - add pin groups for usart3/uart4/spi1/sdmmc2 - add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile) - add stm32h750i-art-pi.dts to support art-pi board - add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot) art-pi board component: - 8MiB qspi flash - 16MiB spi flash - 32MiB sdram - ap6212 wifi&bt&fm the detail board information can be found at: https://art-pi.gitee.io/website/ Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
275 lines
7.9 KiB
Plaintext
275 lines
7.9 KiB
Plaintext
/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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i2c1_pins_a: i2c1-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
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<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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ethernet_rmii: rmii-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 11, AF11)>,
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<STM32_PINMUX('G', 13, AF11)>,
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<STM32_PINMUX('G', 12, AF11)>,
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<STM32_PINMUX('C', 4, AF11)>,
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<STM32_PINMUX('C', 5, AF11)>,
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<STM32_PINMUX('A', 7, AF11)>,
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<STM32_PINMUX('C', 1, AF11)>,
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<STM32_PINMUX('A', 2, AF11)>,
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<STM32_PINMUX('A', 1, AF11)>;
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slew-rate = <2>;
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};
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};
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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pins2{
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <3>;
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drive-open-drain;
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bias-disable;
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};
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};
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sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
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};
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};
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sdmmc1_dir_pins_a: sdmmc1-dir-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
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slew-rate = <3>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2{
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pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
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bias-pull-up;
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};
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};
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sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
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<STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
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<STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
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<STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
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<STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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pins2{
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pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
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slew-rate = <3>;
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drive-open-drain;
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bias-disable;
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};
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};
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sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
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<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
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<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
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<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
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};
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};
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spi1_pins: spi1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 5, AF5)>,
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/* SPI1_CLK */
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<STM32_PINMUX('B', 5, AF5)>;
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/* SPI1_MOSI */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('G', 9, AF5)>;
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/* SPI1_MISO */
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bias-disable;
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};
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};
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uart4_pins: uart4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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usart1_pins: usart1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart2_pins: usart2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
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bias-disable;
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};
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};
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usart3_pins: usart3-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
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<STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
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<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
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bias-disable;
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};
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};
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usbotg_hs_pins_a: usbotg-hs-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
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<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
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<STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
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<STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
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<STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
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<STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
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<STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
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<STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
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<STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
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<STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
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<STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
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<STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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};
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