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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
236 lines
7.2 KiB
C
236 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* emac definitions for keystone2 devices
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef _KEYSTONE_NET_H_
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#define _KEYSTONE_NET_H_
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#include <asm/io.h>
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#include <phy.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* EMAC */
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#ifdef CONFIG_KSNET_NETCP_V1_0
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#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
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#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
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#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
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#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
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#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
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/* Register offsets */
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#define CPGMACSL_REG_CTL 0x04
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#define CPGMACSL_REG_STATUS 0x08
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#define CPGMACSL_REG_RESET 0x0c
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#define CPGMACSL_REG_MAXLEN 0x10
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#elif defined CONFIG_KSNET_NETCP_V1_5
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#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
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#define CPGMACSL_REG_RX_PRI_MAP 0x020
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#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
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#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
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#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
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#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
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/* Register offsets */
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#define CPGMACSL_REG_CTL 0x330
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#define CPGMACSL_REG_STATUS 0x334
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#define CPGMACSL_REG_RESET 0x338
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#define CPGMACSL_REG_MAXLEN 0x024
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#endif
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#define KEYSTONE2_EMAC_GIG_ENABLE
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#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
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/* MDIO module input frequency */
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#ifdef CONFIG_SOC_K2G
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#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk))
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#else
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#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk))
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#endif
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
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#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
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#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
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#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
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#define EMAC_MACCONTROL_GIGFORCE BIT(17)
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#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
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#define EMAC_MIN_ETHERNET_PKT_SIZE 60
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struct mac_sl_cfg {
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u_int32_t max_rx_len; /* Maximum receive packet length. */
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u_int32_t ctl; /* Control bitfield */
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};
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/**
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* Definition: Control bitfields used in the ctl field of mac_sl_cfg
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*/
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#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
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#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
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#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
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#define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
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#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
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#define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
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#define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
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#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
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#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
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#define GMACSL_ENABLE_GIG_MODE BIT(7)
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#define GMACSL_TX_ENABLE_PACE BIT(6)
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#define GMACSL_ENABLE BIT(5)
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#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
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#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
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#define GMACSL_ENABLE_LOOPBACK BIT(1)
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#define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
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/* EMAC SL function return values */
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#define GMACSL_RET_OK 0
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#define GMACSL_RET_INVALID_PORT -1
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#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
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#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
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#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
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/* EMAC SL register definitions */
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#define DEVICE_EMACSL_RESET_POLL_COUNT 100
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/* Soft reset register values */
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#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
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#define CPGMAC_REG_RESET_VAL_RESET BIT(0)
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#define CPGMAC_REG_MAXLEN_LEN 0x3fff
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/* CPSW */
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/* Control bitfields */
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#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
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#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
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#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
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#define CPSW_CTL_P0_ENABLE BIT(2)
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#define CPSW_CTL_VLAN_AWARE BIT(1)
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#define CPSW_CTL_FIFO_LOOPBACK BIT(0)
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#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
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#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
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#ifdef CONFIG_KSNET_NETCP_V1_0
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#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
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#define CPSW_REG_CTL 0x004
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#define CPSW_REG_STAT_PORT_EN 0x00c
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#define CPSW_REG_MAXLEN 0x040
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#define CPSW_REG_ALE_CONTROL 0x608
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#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
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#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
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#elif defined CONFIG_KSNET_NETCP_V1_5
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#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
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#define CPSW_REG_CTL 0x00004
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#define CPSW_REG_STAT_PORT_EN 0x00014
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#define CPSW_REG_MAXLEN 0x01024
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#define CPSW_REG_ALE_CONTROL 0x1e008
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#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
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#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
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#endif
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#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
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#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
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#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
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#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
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#define SWITCH_MAX_PKT_SIZE 9000
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/* SGMII */
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#define SGMII_REG_STATUS_LOCK BIT(4)
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#define SGMII_REG_STATUS_LINK BIT(0)
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#define SGMII_REG_STATUS_AUTONEG BIT(2)
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#define SGMII_REG_CONTROL_AUTONEG BIT(0)
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#define SGMII_REG_CONTROL_MASTER BIT(5)
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#define SGMII_REG_MR_ADV_ENABLE BIT(0)
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#define SGMII_REG_MR_ADV_LINK BIT(15)
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#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
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#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
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#define SGMII_LINK_MAC_MAC_AUTONEG 0
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#define SGMII_LINK_MAC_PHY 1
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#define SGMII_LINK_MAC_MAC_FORCED 2
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#define SGMII_LINK_MAC_FIBER 3
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#define SGMII_LINK_MAC_PHY_FORCED 4
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#ifdef CONFIG_KSNET_NETCP_V1_0
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#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
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#elif defined CONFIG_KSNET_NETCP_V1_5
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#define SGMII_OFFSET(x) ((x) * 0x100)
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#endif
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#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
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#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
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#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
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#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
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#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
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#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
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#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
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#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
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#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
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/* RGMII */
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#define RGMII_REG_STATUS_LINK BIT(0)
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#define RGMII_STATUS_REG (GBETH_BASE + 0x18)
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/* PSS */
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#ifdef CONFIG_KSNET_NETCP_V1_0
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#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
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#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
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#define hw_config_streaming_switch()\
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writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
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#elif defined CONFIG_KSNET_NETCP_V1_5
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#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
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#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
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#define hw_config_streaming_switch()\
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writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
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DEVICE_PSTREAM_CFG_REG_ADDR);\
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writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
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DEVICE_PSTREAM_CFG_REG_ADDR+4);\
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writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
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DEVICE_PSTREAM_CFG_REG_ADDR+8);\
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writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
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DEVICE_PSTREAM_CFG_REG_ADDR+12);
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#endif
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/* EMAC MDIO Registers Structure */
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struct mdio_regs {
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u32 version;
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u32 control;
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u32 alive;
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u32 link;
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u32 linkintraw;
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u32 linkintmasked;
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u32 rsvd0[2];
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u32 userintraw;
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u32 userintmasked;
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u32 userintmaskset;
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u32 userintmaskclear;
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u32 rsvd1[20];
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u32 useraccess0;
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u32 userphysel0;
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u32 useraccess1;
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u32 userphysel1;
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};
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#endif /* _KEYSTONE_NET_H_ */
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