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4a84cf06aa
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
234 lines
4.8 KiB
ArmAsm
234 lines
4.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) ASPEED Technology Inc.
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*/
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#include <config.h>
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#include <asm/armv7.h>
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#include <linux/linkage.h>
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#include <asm/arch/scu_ast2600.h>
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/* SCU register offsets */
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#define SCU_BASE 0x1e6e2000
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#define SCU_PROT_KEY1 (SCU_BASE + 0x000)
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#define SCU_PROT_KEY2 (SCU_BASE + 0x010)
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#define SCU_SMP_BOOT (SCU_BASE + 0x180)
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#define SCU_HWSTRAP1 (SCU_BASE + 0x510)
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#define SCU_CA7_PARITY_CHK (SCU_BASE + 0x820)
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#define SCU_CA7_PARITY_CLR (SCU_BASE + 0x824)
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#define SCU_MMIO_DEC (SCU_BASE + 0xc24)
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/* FMC SPI register offsets */
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#define FMC_BASE 0x1e620000
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#define FMC_CE0_CTRL (FMC_BASE + 0x010)
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#define FMC_SW_RST_CTRL (FMC_BASE + 0x050)
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#define FMC_WDT1_CTRL_MODE (FMC_BASE + 0x060)
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#define FMC_WDT2_CTRL_MODE (FMC_BASE + 0x064)
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/*
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* The SMP mailbox provides a space with few instructions in it
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* for secondary cores to execute on and wait for the signal of
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* SMP core bring up.
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*
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* SMP mailbox
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* +----------------------+
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* | |
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* | mailbox insn. for |
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* | cpuN polling SMP go |
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* | |
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* +----------------------+ 0xC
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* | mailbox ready signal |
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* +----------------------+ 0x8
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* | cpuN GO signal |
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* +----------------------+ 0x4
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* | cpuN entrypoint |
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* +----------------------+ SMP_MAILBOX_BASE
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*/
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#define SMP_MBOX_BASE (SCU_SMP_BOOT)
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#define SMP_MBOX_FIELD_ENTRY (SMP_MBOX_BASE + 0x0)
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#define SMP_MBOX_FIELD_GOSIGN (SMP_MBOX_BASE + 0x4)
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#define SMP_MBOX_FIELD_READY (SMP_MBOX_BASE + 0x8)
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#define SMP_MBOX_FIELD_POLLINSN (SMP_MBOX_BASE + 0xc)
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.macro scu_unlock
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movw r0, #(SCU_UNLOCK_KEY & 0xffff)
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movt r0, #(SCU_UNLOCK_KEY >> 16)
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ldr r1, =SCU_PROT_KEY1
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str r0, [r1]
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ldr r1, =SCU_PROT_KEY2
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str r0, [r1]
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.endm
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.macro timer_init
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ldr r1, =SCU_HWSTRAP1
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ldr r1, [r1]
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and r1, #0x700
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lsr r1, #0x8
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/* 1.2GHz */
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cmp r1, #0x0
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movweq r0, #0x8c00
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movteq r0, #0x4786
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/* 1.6GHz */
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cmp r1, #0x1
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movweq r0, #0x1000
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movteq r0, #0x5f5e
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/* 1.2GHz */
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cmp r1, #0x2
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movweq r0, #0x8c00
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movteq r0, #0x4786
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/* 1.6GHz */
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cmp r1, #0x3
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movweq r0, #0x1000
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movteq r0, #0x5f5e
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/* 800MHz */
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cmp r1, #0x4
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movwge r0, #0x0800
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movtge r0, #0x2faf
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mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ
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.endm
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.globl lowlevel_init
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lowlevel_init:
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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mov pc, lr
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#else
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/* setup ARM arch timer frequency */
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timer_init
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/* reset SMP mailbox as early as possible */
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mov r0, #0x0
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ldr r1, =SMP_MBOX_FIELD_READY
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str r0, [r1]
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/* set ACTLR.SMP to enable cache use */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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/*
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* we treat cpu0 as the primary core and
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* put secondary core (cpuN) to sleep
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*/
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mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register
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ands r0, #0xff @; Mask off, leaving the CPU ID field
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movw r2, #0xab00
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movt r2, #0xabba
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orr r2, r0
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beq do_primary_core_setup
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/* hold cpuN until mailbox is ready */
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poll_mailbox_ready:
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wfe
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ldr r0, =SMP_MBOX_FIELD_READY
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ldr r0, [r0]
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movw r1, #0xcafe
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movt r1, #0xbabe
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cmp r1, r0
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bne poll_mailbox_ready
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/* parameters for relocated SMP go polling insn. */
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ldr r0, =SMP_MBOX_FIELD_GOSIGN
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ldr r1, =SMP_MBOX_FIELD_ENTRY
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/* no return */
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ldr pc, =SMP_MBOX_FIELD_POLLINSN
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do_primary_core_setup:
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scu_unlock
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/* MMIO decode setting */
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ldr r0, =SCU_MMIO_DEC
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mov r1, #0x2000
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str r1, [r0]
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/* enable CA7 cache parity check */
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mov r0, #0
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ldr r1, =SCU_CA7_PARITY_CLR
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str r0, [r1]
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mov r0, #0x1
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ldr r1, =SCU_CA7_PARITY_CHK
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str r0, [r1]
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/* do not fill FMC50[1] if boot from eMMC */
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ldr r0, =SCU_HWSTRAP1
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ldr r1, [r0]
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ands r1, #0x04
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bne skip_fill_wip_bit
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/* fill FMC50[1] for waiting WIP idle */
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mov r0, #0x02
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ldr r1, =FMC_SW_RST_CTRL
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str r0, [r1]
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skip_fill_wip_bit:
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/* disable FMC WDT for SPI address mode detection */
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mov r0, #0
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ldr r1, =FMC_WDT1_CTRL_MODE
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str r0, [r1]
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/* relocate mailbox insn. for cpuN polling SMP go signal */
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adrl r0, mailbox_insn
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adrl r1, mailbox_insn_end
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ldr r2, =#SMP_MBOX_FIELD_POLLINSN
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relocate_mailbox_insn:
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ldr r3, [r0], #0x4
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str r3, [r2], #0x4
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cmp r0, r1
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bne relocate_mailbox_insn
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/* reset SMP go sign */
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mov r0, #0
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ldr r1, =SMP_MBOX_FIELD_GOSIGN
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str r0, [r1]
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/* notify cpuN mailbox is ready */
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movw r0, #0xCAFE
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movt r0, #0xBABE
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ldr r1, =SMP_MBOX_FIELD_READY
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str r0, [r1]
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sev
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/* back to arch calling code */
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mov pc, lr
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/*
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* insn. inside mailbox to poll SMP go signal.
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*
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* Note that as this code will be relocated, any
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* pc-relative assembly should NOT be used.
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*/
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mailbox_insn:
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/*
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* r0 ~ r3 are parameters:
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* r0 = SMP_MBOX_FIELD_GOSIGN
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* r1 = SMP_MBOX_FIELD_ENTRY
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* r2 = per-cpu go sign value
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* r3 = no used now
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*/
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poll_mailbox_smp_go:
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wfe
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ldr r4, [r0]
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cmp r2, r4
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bne poll_mailbox_smp_go
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/* SMP GO signal confirmed, release cpuN */
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ldr pc, [r1]
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mailbox_insn_end:
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/* should never reach */
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b .
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#endif
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