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a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
152 lines
3.6 KiB
ArmAsm
152 lines
3.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the at91rm9200dk board by
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* (C) Copyright 2004
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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#include <config.h>
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_mc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_pio.h>
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#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
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_MTEXT_BASE:
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#undef START_FROM_MEM
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#ifdef START_FROM_MEM
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.word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
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#else
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.word CONFIG_SYS_TEXT_BASE
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#endif
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.globl lowlevel_init
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lowlevel_init:
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ldr r1, =AT91_ASM_PMC_MOR
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/* Main oscillator Enable register */
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#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
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ldr r0, =0x0000FF01 /* Enable main oscillator */
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#else
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ldr r0, =0x0000FF00 /* Disable main oscillator */
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#endif
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str r0, [r1] /*AT91C_CKGR_MOR] */
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/* Add loop to compensate Main Oscillator startup time */
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ldr r0, =0x00000010
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LoopOsc:
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subs r0, r0, #1
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bhi LoopOsc
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/* memory control configuration */
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/* this isn't very elegant, but what the heck */
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ldr r0, =SMRDATA
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ldr r1, _MTEXT_BASE
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sub r0, r0, r1
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ldr r2, =SMRDATAE
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sub r2, r2, r1
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pllloop:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne pllloop
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/* delay - this is all done by guess */
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ldr r0, =0x00010000
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/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
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lock:
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subs r0, r0, #1
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bhi lock
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ldr r0, =SMRDATA1
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ldr r1, _MTEXT_BASE
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sub r0, r0, r1
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ldr r2, =SMRDATA1E
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sub r2, r2, r1
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sdinit:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne sdinit
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/* switch from FastBus to Asynchronous clock mode */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #ARM920T_CONTROL
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mcr p15, 0, r0, c1, c0, 0
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word AT91_ASM_MC_EBI_CFG
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.word CONFIG_SYS_EBI_CFGR_VAL
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.word AT91_ASM_MC_SMC_CSR0
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.word CONFIG_SYS_SMC_CSR0_VAL
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.word AT91_ASM_PMC_PLLAR
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.word CONFIG_SYS_PLLAR_VAL
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.word AT91_ASM_PMC_PLLBR
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.word CONFIG_SYS_PLLBR_VAL
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.word AT91_ASM_PMC_MCKR
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.word CONFIG_SYS_MCKR_VAL
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SMRDATAE:
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/* here there's a delay */
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SMRDATA1:
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.word AT91_ASM_PIOC_ASR
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.word CONFIG_SYS_PIOC_ASR_VAL
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.word AT91_ASM_PIOC_BSR
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.word CONFIG_SYS_PIOC_BSR_VAL
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.word AT91_ASM_PIOC_PDR
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.word CONFIG_SYS_PIOC_PDR_VAL
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.word AT91_ASM_MC_EBI_CSA
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.word CONFIG_SYS_EBI_CSA_VAL
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.word AT91_ASM_MC_SDRAMC_CR
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.word CONFIG_SYS_SDRC_CR_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL1
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL2
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.word CONFIG_SYS_SDRAM1
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_TR
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.word CONFIG_SYS_SDRC_TR_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL3
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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SMRDATA1E:
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/* SMRDATA1 is 176 bytes long */
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#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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