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8bad34a709
SAMA7G5 supports slew rate configuration. Adapt the driver for this. For switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Atmel Corporation.
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* Wenyou Yang <wenyou.yang@atmel.com>
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*/
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#ifndef __ATMEL_PIO4_H
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#define __ATMEL_PIO4_H
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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struct atmel_pio4_port {
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u32 mskr; /* 0x00 PIO Mask Register */
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u32 cfgr; /* 0x04 PIO Configuration Register */
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u32 pdsr; /* 0x08 PIO Pin Data Status Register */
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u32 locksr; /* 0x0C PIO Lock Status Register */
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u32 sodr; /* 0x10 PIO Set Output Data Register */
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u32 codr; /* 0x14 PIO Clear Output Data Register */
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u32 odsr; /* 0x18 PIO Output Data Status Register */
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u32 reserved0;
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u32 ier; /* 0x20 PIO Interrupt Enable Register */
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u32 idr; /* 0x24 PIO Interrupt Disable Register */
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u32 imr; /* 0x28 PIO Interrupt Mask Register */
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u32 isr; /* 0x2C PIO Interrupt Status Register */
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u32 reserved1[3];
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u32 iofr; /* 0x3C PIO I/O Freeze Register */
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};
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#endif
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/*
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* PIO Configuration Register Fields
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*/
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#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
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#define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0)
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#define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0)
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#define ATMEL_PIO_DIR_MASK BIT(8)
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#define ATMEL_PIO_PUEN_MASK BIT(9)
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#define ATMEL_PIO_PDEN_MASK BIT(10)
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#define ATMEL_PIO_SR BIT(11)
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#define ATMEL_PIO_IFEN_MASK BIT(12)
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#define ATMEL_PIO_IFSCEN_MASK BIT(13)
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#define ATMEL_PIO_OPD_MASK BIT(14)
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#define ATMEL_PIO_SCHMITT_MASK BIT(15)
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#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
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#define ATMEL_PIO_DRVSTR_LO (1 << 16)
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#define ATMEL_PIO_DRVSTR_ME (2 << 16)
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#define ATMEL_PIO_DRVSTR_HI (3 << 16)
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#define ATMEL_PIO_DRVSTR_OFFSET 16
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#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
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#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
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#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
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#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
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#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
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#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
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#define ATMEL_PIO_NPINS_PER_BANK 32
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#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
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#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
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#define ATMEL_PIO_BANK_OFFSET 0x40
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#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
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#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
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#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
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#define AT91_PIO_PORTA 0x0
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#define AT91_PIO_PORTB 0x1
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#define AT91_PIO_PORTC 0x2
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#define AT91_PIO_PORTD 0x3
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int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config);
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int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value);
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int atmel_pio4_get_pio_input(u32 port, u32 pin);
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#endif
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