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de77811589
Restructure clock manager driver in the preparation to support A10. Move the Gen5 specific code to _gen5 files. - Change all uint32_t to u32 and change to use macro BIT(n) for bit shift. - Check return value from wait_for_bit(). So change return type to int for cm_write_with_phase() and cm_basic_init(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
20 lines
415 B
C
20 lines
415 B
C
/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCK_MANAGER_H_
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#define _CLOCK_MANAGER_H_
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#ifndef __ASSEMBLER__
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void cm_wait_for_lock(u32 mask);
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int cm_wait_for_fsm(void);
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void cm_print_clock_quick_summary(void);
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/clock_manager_gen5.h>
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#endif
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#endif /* _CLOCK_MANAGER_H_ */
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