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154 lines
3.8 KiB
C
154 lines
3.8 KiB
C
/*
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* (C) Copyright 2004, Freescale Inc.
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* TsiChung Liew, Tsi-Chung.Liew@freescale.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8220.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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void setupBat (ulong size)
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{
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ulong batu, batl;
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int blocksize = 0;
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/* Flash 0 */
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#if defined (CFG_AMD_BOOT)
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batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
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#else
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batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
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#endif
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batl = CFG_FLASH0_BASE | 0x22;
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write_bat (IBAT0, batu, batl);
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write_bat (DBAT0, batu, batl);
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/* Flash 1 */
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#if defined (CFG_AMD_BOOT)
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batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
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#else
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batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
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#endif
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batl = CFG_FLASH1_BASE | 0x22;
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write_bat (IBAT1, batu, batl);
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write_bat (DBAT1, batu, batl);
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/* CPLD */
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batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
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batl = CFG_CPLD_BASE | 0x22;
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write_bat (IBAT2, 0, 0);
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write_bat (DBAT2, batu, batl);
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/* FPGA */
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batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
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batl = CFG_FPGA_BASE | 0x22;
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write_bat (IBAT3, 0, 0);
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write_bat (DBAT3, batu, batl);
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/* MBAR - Data only */
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batu = CFG_MBAR | BPP_RW | BPP_RX;
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batl = CFG_MBAR | 0x22;
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mtspr (IBAT4L, 0);
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mtspr (IBAT4U, 0);
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mtspr (DBAT4L, batl);
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mtspr (DBAT4U, batu);
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/* MBAR - SRAM */
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batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
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batl = CFG_SRAM_BASE | 0x42;
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mtspr (IBAT5L, batl);
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mtspr (IBAT5U, batu);
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mtspr (DBAT5L, batl);
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mtspr (DBAT5U, batu);
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if (size <= 0x800000) /* 8MB */
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blocksize = BL_8M << 2;
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else if (size <= 0x1000000) /* 16MB */
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blocksize = BL_16M << 2;
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else if (size <= 0x2000000) /* 32MB */
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blocksize = BL_32M << 2;
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else if (size <= 0x4000000) /* 64MB */
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blocksize = BL_64M << 2;
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else if (size <= 0x8000000) /* 128MB */
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blocksize = BL_128M << 2;
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else if (size <= 0x10000000) /* 256MB */
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blocksize = BL_256M << 2;
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/* Memory */
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batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
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batl = CFG_SDRAM_BASE | 0x42;
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mtspr (IBAT6L, batl);
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mtspr (IBAT6U, batu);
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mtspr (DBAT6L, batl);
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mtspr (DBAT6U, batu);
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/* memory size is less than 256MB */
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if (size <= 0x10000000) {
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/* Nothing */
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batu = 0;
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batl = 0;
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} else {
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size -= 0x10000000;
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if (size <= 0x800000) /* 8MB */
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blocksize = BL_8M << 2;
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else if (size <= 0x1000000) /* 16MB */
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blocksize = BL_16M << 2;
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else if (size <= 0x2000000) /* 32MB */
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blocksize = BL_32M << 2;
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else if (size <= 0x4000000) /* 64MB */
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blocksize = BL_64M << 2;
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else if (size <= 0x8000000) /* 128MB */
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blocksize = BL_128M << 2;
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else if (size <= 0x10000000) /* 256MB */
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blocksize = BL_256M << 2;
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batu = (CFG_SDRAM_BASE +
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0x10000000) | blocksize | BPP_RW | BPP_RX;
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batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
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}
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mtspr (IBAT7L, batl);
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mtspr (IBAT7U, batu);
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mtspr (DBAT7L, batl);
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mtspr (DBAT7U, batu);
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}
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long int initdram (int board_type)
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{
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ulong size;
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size = dramSetup ();
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/* if iCache ad dCache is defined */
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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/* setupBat(size);*/
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#endif
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return size;
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}
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int checkboard (void)
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{
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puts ("Board: Alaska MPC8220 Evaluation Board\n");
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return 0;
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}
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