mirror of
https://github.com/smaeul/u-boot.git
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319 lines
10 KiB
C
319 lines
10 KiB
C
/*
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* (C) Copyright 2003
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* AMIRIX Systems Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <pci.h>
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#define PCI_MEM_82559ER_CSR_BASE 0x30200000
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#define PCI_IO_82559ER_CSR_BASE 0x40000200
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/** AP1100 specific values */
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#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
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#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
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#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
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#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
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#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
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#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
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#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
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#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
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/* static int G_verbosity_level = 1; */
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#define G_verbosity_level 1
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void write1 (unsigned long addr, unsigned char val)
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{
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volatile unsigned char *p = (volatile unsigned char *) addr;
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if (G_verbosity_level > 1)
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printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
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val);
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*p = val;
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asm ("eieio");
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}
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unsigned char read1 (unsigned long addr)
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{
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unsigned char val;
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volatile unsigned char *p = (volatile unsigned char *) addr;
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if (G_verbosity_level > 1)
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printf ("read1: addr=%08x ", (unsigned int) addr);
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val = *p;
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asm ("eieio");
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if (G_verbosity_level > 1)
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printf ("val=%08x\n", val);
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return val;
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}
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void write2 (unsigned long addr, unsigned short val)
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{
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volatile unsigned short *p = (volatile unsigned short *) addr;
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if (G_verbosity_level > 1)
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printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
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(unsigned int) addr, val,
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((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
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*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
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asm ("eieio");
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}
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unsigned short read2 (unsigned long addr)
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{
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unsigned short val;
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volatile unsigned short *p = (volatile unsigned short *) addr;
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if (G_verbosity_level > 1)
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printf ("read2: addr=%08x ", (unsigned int) addr);
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val = *p;
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val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
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asm ("eieio");
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if (G_verbosity_level > 1)
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printf ("*p=%04x -> val=%04x\n",
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((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
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return val;
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}
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void write4 (unsigned long addr, unsigned long val)
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{
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volatile unsigned long *p = (volatile unsigned long *) addr;
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if (G_verbosity_level > 1)
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printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
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(unsigned int) addr, (unsigned int) val,
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(unsigned int) (((val & 0xFF000000) >> 24) |
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((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) |
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((val & 0x0000FF00) << 8)));
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*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
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asm ("eieio");
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}
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unsigned long read4 (unsigned long addr)
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{
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unsigned long val;
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volatile unsigned long *p = (volatile unsigned long *) addr;
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if (G_verbosity_level > 1)
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printf ("read4: addr=%08x", (unsigned int) addr);
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val = *p;
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val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
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asm ("eieio");
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if (G_verbosity_level > 1)
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printf ("*p=%04x -> val=%04x\n",
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(unsigned int) (((val & 0xFF000000) >> 24) |
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((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) |
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((val & 0x0000FF00) << 8)),
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(unsigned int) val);
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return val;
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}
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void write4be (unsigned long addr, unsigned long val)
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{
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volatile unsigned long *p = (volatile unsigned long *) addr;
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if (G_verbosity_level > 1)
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printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
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(unsigned int) val);
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*p = val;
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asm ("eieio");
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}
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/** One byte configuration write on PSII.
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* Currently fixes destination PCI bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Address of location for received byte.
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* @return Always Zero.
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*/
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static int psII_read_config_byte (struct pci_controller *hose,
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pci_dev_t dev, int reg, u8 * val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
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return (0);
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}
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/** One byte configuration write on PSII.
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* Currently fixes destination bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Output byte.
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* @return Always Zero.
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*/
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static int psII_write_config_byte (struct pci_controller *hose,
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pci_dev_t dev, int reg, u8 val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
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return (0);
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}
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/** One word (16 bit) configuration read on PSII.
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* Currently fixes destination PCI bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Address of location for received word.
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* @return Always Zero.
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*/
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static int psII_read_config_word (struct pci_controller *hose,
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pci_dev_t dev, int reg, u16 * val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
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return (0);
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}
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/** One word (16 bit) configuration write on PSII.
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* Currently fixes destination bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Output word.
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* @return Always Zero.
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*/
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static int psII_write_config_word (struct pci_controller *hose,
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pci_dev_t dev, int reg, u16 val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
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return (0);
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}
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/** One DWord (32 bit) configuration read on PSII.
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* Currently fixes destination PCI bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Address of location for received byte.
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* @return Always Zero.
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*/
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static int psII_read_config_dword (struct pci_controller *hose,
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pci_dev_t dev, int reg, u32 * val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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*val = read4 (PSII_CONFIG_DATA);
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return (0);
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}
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/** One DWord (32 bit) configuration write on PSII.
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* Currently fixes destination bus to PCI2, onboard
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* pci.
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* @param hose PCI Host controller information. Ignored.
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* @param dev Encoded PCI device/Bus and Function value.
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* @param reg PCI Configuration register number.
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* @param val Output Dword.
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* @return Always Zero.
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*/
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static int psII_write_config_dword (struct pci_controller *hose,
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pci_dev_t dev, int reg, u32 val)
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{
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write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
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(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
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write4 (PSII_CONFIG_DATA, (unsigned long) val);
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return (0);
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}
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static struct pci_config_table ap1000_config_table[] = {
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#ifdef CONFIG_AP1000
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
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PCI_FUNC (CFG_ETH_DEV_FN),
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pci_cfgfunc_config_device,
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{CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
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#endif
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{}
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};
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static struct pci_controller psII_hose = {
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config_table:ap1000_config_table,
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};
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void pci_init_board (void)
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{
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struct pci_controller *hose = &psII_hose;
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/*
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* Register the hose
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*/
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region (hose->regions + 0,
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AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
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AP1000_SYS_MEM_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI Memory space */
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pci_set_region (hose->regions + 1,
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PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
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PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
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/* No IO Memory space - for now */
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pci_set_ops (hose,
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psII_read_config_byte,
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psII_read_config_word,
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psII_read_config_dword,
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psII_write_config_byte,
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psII_write_config_word, psII_write_config_dword);
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hose->region_count = 2;
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pci_register_hose (hose);
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hose->last_busno = pci_hose_scan (hose);
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}
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