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dd1033e4e0
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __ASM_MACH_MSCC_IOREMAP_H
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#define __ASM_MACH_MSCC_IOREMAP_H
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#include <linux/types.h>
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#include <mach/common.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
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phys_addr_t size)
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{
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return phys_addr;
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}
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static inline int is_vcoreiii_internal_registers(phys_addr_t offset)
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{
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if ((offset >= MSCC_IO_ORIGIN1_OFFSET &&
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offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) ||
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(offset >= MSCC_IO_ORIGIN2_OFFSET &&
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offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE)))
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return 1;
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return 0;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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if (is_vcoreiii_internal_registers(offset))
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return (void __iomem *)offset;
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return NULL;
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return is_vcoreiii_internal_registers((unsigned long)addr);
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}
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#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
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#endif /* __ASM_MACH_MSCC_IOREMAP_H */
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