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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments
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*
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Moahmmed Khasim <khasim@ti.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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static ulong timestamp;
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static ulong lastinc;
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static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
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/*
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* Nothing really to do with interrupts, just starts up a counter.
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* We run the counter with 13MHz, divided by 8, resulting in timer
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* frequency of 1.625MHz. With 32bit counter register, counter
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* overflows in ~44min
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*/
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/* 13MHz / 8 = 1.625MHz */
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#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
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#define TIMER_LOAD_VAL 0xffffffff
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int timer_init(void)
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{
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/* start the counter ticking up, reload value on overflow */
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writel(TIMER_LOAD_VAL, &timer_base->tldr);
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/* enable timer */
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writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
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&timer_base->tclr);
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reset_timer_masked(); /* init the timestamp and lastinc value */
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return 0;
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}
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/*
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* timer without interrupts
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*/
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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/* delay x useconds */
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void __udelay(unsigned long usec)
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{
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long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
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unsigned long now, last = readl(&timer_base->tcrr);
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while (tmo > 0) {
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now = readl(&timer_base->tcrr);
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if (last > now) /* count up timer overflow */
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tmo -= TIMER_LOAD_VAL - last + now;
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else
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tmo -= now - last;
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last = now;
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}
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}
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void reset_timer_masked(void)
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{
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/* reset time, capture current incrementer value time */
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lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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ulong get_timer_masked(void)
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{
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/* current tick value */
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ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp fordward with absoulte diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
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- lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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