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	Add i.MX8M support. Because i.MX8M use SiP call trap to Arm Trusted Firmware to handle M4, so use #ifdef to avoid build error on i.MX6/7. Signed-off-by: Peng Fan <peng.fan@nxp.com>
		
			
				
	
	
		
			98 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			98 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2016 Freescale Semiconductor, Inc.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <asm/io.h>
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| #include <asm/mach-imx/sys_proto.h>
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| #include <command.h>
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| #include <imx_sip.h>
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| #include <linux/compiler.h>
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| 
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| int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
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| {
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| 	ulong stack, pc;
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| 
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| 	if (!boot_private_data)
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| 		return -EINVAL;
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| 
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| 	stack = *(ulong *)boot_private_data;
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| 	pc = *(ulong *)(boot_private_data + 4);
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| 
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| 	/* Set the stack and pc to M4 bootROM */
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| 	writel(stack, M4_BOOTROM_BASE_ADDR);
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| 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
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| 
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| 	/* Enable M4 */
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| #ifdef CONFIG_MX8M
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| 	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
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| #else
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| 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
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| 			SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
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| #endif
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| 
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| 	return 0;
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| }
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| 
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| int arch_auxiliary_core_check_up(u32 core_id)
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| {
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| #ifdef CONFIG_MX8M
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| 	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
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| #else
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| 	unsigned int val;
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| 
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| 	val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
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| 
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| 	if (val & SRC_M4C_NON_SCLR_RST_MASK)
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| 		return 0;  /* assert in reset */
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| 
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| 	return 1;
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| #endif
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| }
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| 
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| /*
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|  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
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|  * the reset vector at the head for the image, with SP and PC
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|  * as the first two words.
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|  *
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|  * Per the cortex-M reference manual, the reset vector of M4 needs
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|  * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
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|  * of that vector.  So to boot M4, the A core must build the M4's reset
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|  * vector with getting the PC and SP from image and filling them to
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|  * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
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|  * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
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|  * accessing the M4 TCMUL.
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|  */
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| static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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| {
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| 	ulong addr;
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| 	int ret, up;
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| 
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| 	if (argc < 2)
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| 		return CMD_RET_USAGE;
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| 
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| 	up = arch_auxiliary_core_check_up(0);
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| 	if (up) {
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| 		printf("## Auxiliary core is already up\n");
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| 		return CMD_RET_SUCCESS;
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| 	}
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| 
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| 	addr = simple_strtoul(argv[1], NULL, 16);
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| 
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| 	printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
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| 
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| 	ret = arch_auxiliary_core_up(0, addr);
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| 	if (ret)
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| 		return CMD_RET_FAILURE;
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| 
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| 	return CMD_RET_SUCCESS;
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| }
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| 
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| U_BOOT_CMD(
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| 	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
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| 	"Start auxiliary core",
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| 	""
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| );
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