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552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
88 lines
1.5 KiB
C
88 lines
1.5 KiB
C
/*
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* (C) Copyright 2014
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* Gabriel Huau <contact@huau-gabriel.fr>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/imx-regs.h>
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#define MAX_CPUS 4
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static struct src *src = (struct src *)SRC_BASE_ADDR;
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static uint32_t cpu_reset_mask[MAX_CPUS] = {
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0, /* We don't really want to modify the cpu0 */
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SRC_SCR_CORE_1_RESET_MASK,
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SRC_SCR_CORE_2_RESET_MASK,
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SRC_SCR_CORE_3_RESET_MASK
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};
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static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
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0, /* We don't really want to modify the cpu0 */
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SRC_SCR_CORE_1_ENABLE_MASK,
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SRC_SCR_CORE_2_ENABLE_MASK,
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SRC_SCR_CORE_3_ENABLE_MASK
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};
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int cpu_reset(int nr)
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{
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/* Software reset of the CPU N */
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src->scr |= cpu_reset_mask[nr];
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return 0;
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}
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int cpu_status(int nr)
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{
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printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
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return 0;
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}
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int cpu_release(int nr, int argc, char *const argv[])
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{
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uint32_t boot_addr;
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boot_addr = simple_strtoul(argv[0], NULL, 16);
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switch (nr) {
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case 1:
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src->gpr3 = boot_addr;
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break;
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case 2:
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src->gpr5 = boot_addr;
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break;
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case 3:
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src->gpr7 = boot_addr;
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break;
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default:
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return 1;
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}
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/* CPU N is ready to start */
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src->scr |= cpu_ctrl_mask[nr];
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return 0;
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}
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int is_core_valid(unsigned int core)
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{
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uint32_t nr_cores = get_nr_cpus();
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if (core > nr_cores)
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return 0;
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return 1;
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}
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int cpu_disable(int nr)
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{
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/* Disable the CPU N */
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src->scr &= ~cpu_ctrl_mask[nr];
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return 0;
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}
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