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51100cfcca
This patch provides support for SPI emulated over SSP for Marvell Armada100 SOC. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __ARMADA100_SPI_H_
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#define __ARMADA100_SPI_H_
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#include <asm/arch/armada100.h>
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#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
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#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
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/*
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* SSP Serial Port Registers
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* refer Appendix A.26
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*/
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struct ssp_reg {
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u32 sscr0; /* SSP Control Register 0 - 0x000 */
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u32 sscr1; /* SSP Control Register 1 - 0x004 */
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u32 sssr; /* SSP Status Register - 0x008 */
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u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
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u32 ssdr; /* SSP Data Register - 0x010 */
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u32 pad1[5];
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u32 ssto; /* SSP Timeout Register - 0x028 */
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u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
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u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
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u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
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u32 sstss; /* SSP Timeslot Status Register - 0x038 */
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};
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#define DEFAULT_WORD_LEN 8
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#define SSP_FLUSH_NUM 0x2000
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#define RX_THRESH_DEF 8
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#define TX_THRESH_DEF 8
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#define TIMEOUT_DEF 1000
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#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
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#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
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#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
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#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
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setting */
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#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
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#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
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#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
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#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
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#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
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#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
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#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
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Interrupt enable */
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#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
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#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF 0x30 /* FRame Format (mask) */
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#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
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Peripheral Interface */
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#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
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Serial Protocol (SSP) */
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#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
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#define SSCR0_ECS (1 << 6) /* External clock select */
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#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
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Enable */
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#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
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#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
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#define SSSR_BSY (1 << 4) /* SSP Busy */
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#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
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#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
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#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
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#endif /* __ARMADA100_SPI_H_ */
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