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145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* This test performs testing of FPGA SCRATCH register,
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* gets FPGA version and run get_ram_size() on FPGA memory
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*/
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#include <post.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FPGA_SCRATCH_REG 0xC4000050
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#define FPGA_VERSION_REG 0xC4000040
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#define FPGA_RAM_START 0xC4200000
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#define FPGA_RAM_END 0xC4203FFF
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#define FPGA_STAT 0xC400000C
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#if CONFIG_POST & CFG_POST_BSPEC3
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/* Testpattern for fpga memorytest */
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static uint pattern[] = {
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0x55555555,
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0xAAAAAAAA,
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0xAA5555AA,
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0x55AAAA55,
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0x0
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};
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static int one_scratch_test(uint value)
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{
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uint read_value;
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int ret = 0;
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out_be32((void *)FPGA_SCRATCH_REG, value);
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/* read other location (protect against data lines capacity) */
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ret = in_be16((void *)FPGA_VERSION_REG);
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/* verify test pattern */
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read_value = in_be32((void *)FPGA_SCRATCH_REG);
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if (read_value != value) {
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post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
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value, read_value);
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ret = 1;
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}
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return ret;
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}
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/* FPGA Memory-pattern-test */
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static int fpga_mem_test(void * address)
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{
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int ret = 1;
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uint read_value;
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uint old_value;
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uint i = 0;
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/* save content */
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old_value = in_be32(address);
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while (pattern[i] != 0) {
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out_be32(address, pattern[i]);
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/* read other location (protect against data lines capacity) */
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ret = in_be16((void *)FPGA_VERSION_REG);
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/* verify test pattern */
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read_value = in_be32(address);
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if (read_value != pattern[i]) {
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post_log("FPGA Memory test failed.");
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post_log(" write %08X, read %08X at address %08X\n",
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pattern[i], read_value, address);
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ret = 1;
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goto out;
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}
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i++;
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}
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ret = 0;
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out:
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out_be32(address, old_value);
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return ret;
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}
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/* Verify FPGA, get version & memory size */
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int fpga_post_test(int flags)
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{
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uint address;
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uint old_value;
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ushort version;
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uint read_value;
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int ret = 0;
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post_log("\n");
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old_value = in_be32((void *)FPGA_SCRATCH_REG);
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if (one_scratch_test(0x55555555))
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ret = 1;
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if (one_scratch_test(0xAAAAAAAA))
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ret = 1;
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out_be32((void *)FPGA_SCRATCH_REG, old_value);
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version = in_be16((void *)FPGA_VERSION_REG);
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post_log("FPGA : version %u.%u\n",
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(version >> 8) & 0xFF, version & 0xFF);
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/* Enable write to FPGA RAM */
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out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
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read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
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post_log("FPGA RAM size: %d bytes\n", read_value);
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for (address = 0; address < 0x1000; address++) {
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if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
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ret = 1;
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goto out;
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}
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}
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out:
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return ret;
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}
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#endif /* CONFIG_POST & CFG_POST_BSPEC3 */
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