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69ef98b209
Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
86 lines
1.6 KiB
Plaintext
86 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include "stm32mp157c-dk2.dts"
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#include "stm32mp15-scmi.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
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compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
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reserved-memory {
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optee@de000000 {
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reg = <0xde000000 0x2000000>;
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no-map;
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};
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};
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};
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&cpu0 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cpu1 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cryp1 {
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clocks = <&scmi_clk CK_SCMI_CRYP1>;
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resets = <&scmi_reset RST_SCMI_CRYP1>;
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};
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&dsi {
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phy-dsi-supply = <&scmi_reg18>;
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clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
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};
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&gpioz {
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clocks = <&scmi_clk CK_SCMI_GPIOZ>;
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};
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&hash1 {
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clocks = <&scmi_clk CK_SCMI_HASH1>;
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resets = <&scmi_reset RST_SCMI_HASH1>;
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};
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&i2c4 {
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clocks = <&scmi_clk CK_SCMI_I2C4>;
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resets = <&scmi_reset RST_SCMI_I2C4>;
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};
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&iwdg2 {
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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};
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&mdma1 {
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resets = <&scmi_reset RST_SCMI_MDMA>;
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};
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&mlahb {
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resets = <&scmi_reset RST_SCMI_MCU>;
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};
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&rcc {
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compatible = "st,stm32mp1-rcc-secure", "syscon";
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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&rng1 {
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clocks = <&scmi_clk CK_SCMI_RNG1>;
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resets = <&scmi_reset RST_SCMI_RNG1>;
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};
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&rtc {
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clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
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};
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