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	Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers instead of board GPIO initialization. Remove stm32_gpio.c which is no more used and migrate structs stm32_gpio_regs and stm32_gpio_priv into arch-stm32f4/gpio.h to not break compilation. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
		
			
				
	
	
		
			55 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			55 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2011
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|  * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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|  *
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|  * (C) Copyright 2015
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|  * Kamil Lulko, <kamil.lulko@gmail.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #ifndef _MACH_STM32_H_
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| #define _MACH_STM32_H_
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| 
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| /*
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|  * Peripheral memory map
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|  */
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| #define STM32_SYSMEM_BASE	0x1FFF0000
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| #define STM32_PERIPH_BASE	0x40000000
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| #define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
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| #define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
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| #define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
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| #define STM32_AHB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x10000000)
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| 
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| #define STM32_BUS_MASK		0xFFFF0000
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| 
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| /*
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|  * Register maps
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|  */
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| struct stm32_u_id_regs {
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| 	u32 u_id_low;
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| 	u32 u_id_mid;
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| 	u32 u_id_high;
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| };
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| 
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| /*
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|  * Registers access macros
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|  */
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| #define STM32_U_ID_BASE		(STM32_SYSMEM_BASE + 0x7A10)
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| #define STM32_U_ID		((struct stm32_u_id_regs *)STM32_U_ID_BASE)
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| 
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| #define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x3800)
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| #define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
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| 
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| #define FLASH_CNTL_BASE		(STM32_AHB1PERIPH_BASE + 0x3C00)
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| 
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| static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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| 	[0 ... 3] =	16 * 1024,
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| 	[4] =		64 * 1024,
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| 	[5 ... 11] =	128 * 1024
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| };
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| 
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| void stm32_flash_latency_cfg(int latency);
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| 
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| #endif /* _MACH_STM32_H_ */
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