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c4b4500910
The iproc architecture code is present in several Broadcom chip architectures, including Cygnus and NSP. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/*
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* Copyright 2014 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SYSMAP_H
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#define __SYSMAP_H
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#define IHOST_PROC_CLK_PLLARMA 0X19000C00
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#define IHOST_PROC_CLK_PLLARMB 0X19000C04
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#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24
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#define IHOST_PROC_CLK_WR_ACCESS 0X19000000
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#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
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#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31
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#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24
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#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16
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#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8
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#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
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#define IHOST_PROC_CLK_POLICY_CTL__GO 0
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#define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1
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#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
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#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH 20
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#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK 28
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#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0
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#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8
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#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1
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#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
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#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
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#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204
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#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210
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#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300
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#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400
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#define IPROC_CLKCT_HDELAY_SW_EN 0x00000303
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#define IPROC_REG_WRITE_ACCESS 0x00a5a501
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#define IPROC_PERIPH_BASE 0x19020000
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#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100)
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#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
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#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600)
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#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000)
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#define PLL_AXI_CLK 0x1DCD6500
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#endif /* __SYSMAP_H */
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