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fe772ebd28
Since all the clocks are defined common, and has the same logic to get the frequencies, use a common definition for for clk_get_rate(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
36 lines
993 B
C
36 lines
993 B
C
/*
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* K2E: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2E_H
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#define __ASM_ARCH_CLOCK_K2E_H
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#define PLLSET_CMD_LIST "<pa|ddr3>"
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#define KS2_CLK1_6 sys_clk0_6_clk
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#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
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#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
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#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
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#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
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#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
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#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
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#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
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#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
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#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
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#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
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#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
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#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
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/* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
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#define DEV_SUPPORTED_SPEEDS 0xFFF
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#define ARM_SUPPORTED_SPEEDS 0
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#endif
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