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76b3f195e9
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
47 lines
1.5 KiB
C
47 lines
1.5 KiB
C
/*
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* K2L: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2L_H
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#define __ASM_ARCH_CLOCK_K2L_H
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#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
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#define KS2_CLK1_6 sys_clk0_6_clk
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#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
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#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
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#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
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#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
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#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
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#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
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#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
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#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
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#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
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#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
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#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
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#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
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#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
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#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
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#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
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#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
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#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
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#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
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#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
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#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
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#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
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#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
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/* k2l DEV supports 800, 1000, 1200 MHz */
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#define DEV_SUPPORTED_SPEEDS 0x383
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/* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
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#define ARM_SUPPORTED_SPEEDS 0x3ef
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#endif
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