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ae3527f088
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
40 lines
699 B
C
40 lines
699 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Based on arch/mips/include/asm/spl.h.
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*
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* (C) Copyright 2012
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* Texas Instruments, <www.ti.com>
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*/
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#ifndef _ASM_RISCV_SPL_H_
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#define _ASM_RISCV_SPL_H_
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enum {
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BOOT_DEVICE_RAM,
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BOOT_DEVICE_MMC1,
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BOOT_DEVICE_MMC2,
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BOOT_DEVICE_MMC2_2,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_ONENAND,
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BOOT_DEVICE_NOR,
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BOOT_DEVICE_UART,
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BOOT_DEVICE_SPI,
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BOOT_DEVICE_USB,
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BOOT_DEVICE_SATA,
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BOOT_DEVICE_I2C,
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BOOT_DEVICE_BOARD,
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BOOT_DEVICE_DFU,
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BOOT_DEVICE_XIP,
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BOOT_DEVICE_BOOTROM,
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BOOT_DEVICE_SMH,
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BOOT_DEVICE_NONE
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};
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/**
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* spl_board_init_f() - initialize board in the SPL phase
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*
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* Return: 0 if succeeded, -ve on error
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*/
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int spl_board_init_f(void);
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#endif
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