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01c8b664d2
Add support of stm32mp13 DT bindings of clock and reset. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
230 lines
4.4 KiB
C
230 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
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#define _DT_BINDINGS_STM32MP13_CLKS_H_
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/* OSCILLATOR clocks */
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#define CK_HSE 0
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#define CK_CSI 1
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#define CK_LSI 2
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#define CK_LSE 3
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#define CK_HSI 4
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#define CK_HSE_DIV2 5
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/* PLL */
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#define PLL1 6
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#define PLL2 7
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#define PLL3 8
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#define PLL4 9
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/* ODF */
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#define PLL1_P 10
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#define PLL1_Q 11
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#define PLL1_R 12
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#define PLL2_P 13
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#define PLL2_Q 14
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#define PLL2_R 15
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#define PLL3_P 16
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#define PLL3_Q 17
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#define PLL3_R 18
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#define PLL4_P 19
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#define PLL4_Q 20
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#define PLL4_R 21
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#define PCLK1 22
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#define PCLK2 23
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#define PCLK3 24
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#define PCLK4 25
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#define PCLK5 26
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#define PCLK6 27
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/* SYSTEM CLOCK */
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#define CK_PER 28
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#define CK_MPU 29
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#define CK_AXI 30
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#define CK_MLAHB 31
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/* BASE TIMER */
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#define CK_TIMG1 32
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#define CK_TIMG2 33
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#define CK_TIMG3 34
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/* AUX */
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#define RTC 35
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/* TRACE & DEBUG clocks */
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#define CK_DBG 36
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#define CK_TRACE 37
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/* MCO clocks */
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#define CK_MCO1 38
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#define CK_MCO2 39
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/* IP clocks */
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#define SYSCFG 40
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#define VREF 41
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#define DTS 42
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#define PMBCTRL 43
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#define HDP 44
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#define IWDG2 45
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#define STGENRO 46
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#define USART1 47
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#define RTCAPB 48
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#define TZC 49
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#define TZPC 50
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#define IWDG1 51
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#define BSEC 52
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#define DMA1 53
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#define DMA2 54
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#define DMAMUX1 55
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#define DMAMUX2 56
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#define GPIOA 57
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#define GPIOB 58
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#define GPIOC 59
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#define GPIOD 60
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#define GPIOE 61
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#define GPIOF 62
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#define GPIOG 63
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#define GPIOH 64
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#define GPIOI 65
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#define CRYP1 66
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#define HASH1 67
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#define BKPSRAM 68
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#define MDMA 69
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#define CRC1 70
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#define USBH 71
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#define DMA3 72
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#define TSC 73
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#define PKA 74
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#define AXIMC 75
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#define MCE 76
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#define ETH1TX 77
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#define ETH2TX 78
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#define ETH1RX 79
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#define ETH2RX 80
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#define ETH1MAC 81
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#define ETH2MAC 82
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#define ETH1STP 83
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#define ETH2STP 84
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/* IP clocks with parents */
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#define SDMMC1_K 85
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#define SDMMC2_K 86
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#define ADC1_K 87
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#define ADC2_K 88
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#define FMC_K 89
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#define QSPI_K 90
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#define RNG1_K 91
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#define USBPHY_K 92
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#define STGEN_K 93
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#define SPDIF_K 94
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#define SPI1_K 95
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#define SPI2_K 96
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#define SPI3_K 97
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#define SPI4_K 98
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#define SPI5_K 99
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#define I2C1_K 100
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#define I2C2_K 101
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#define I2C3_K 102
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#define I2C4_K 103
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#define I2C5_K 104
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#define TIM2_K 105
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#define TIM3_K 106
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#define TIM4_K 107
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#define TIM5_K 108
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#define TIM6_K 109
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#define TIM7_K 110
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#define TIM12_K 111
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#define TIM13_K 112
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#define TIM14_K 113
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#define TIM1_K 114
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#define TIM8_K 115
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#define TIM15_K 116
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#define TIM16_K 117
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#define TIM17_K 118
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#define LPTIM1_K 119
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#define LPTIM2_K 120
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#define LPTIM3_K 121
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#define LPTIM4_K 122
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#define LPTIM5_K 123
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#define USART1_K 124
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#define USART2_K 125
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#define USART3_K 126
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#define UART4_K 127
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#define UART5_K 128
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#define USART6_K 129
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#define UART7_K 130
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#define UART8_K 131
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#define DFSDM_K 132
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#define FDCAN_K 133
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#define SAI1_K 134
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#define SAI2_K 135
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#define ADFSDM_K 136
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#define USBO_K 137
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#define LTDC_PX 138
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#define ETH1CK_K 139
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#define ETH1PTP_K 140
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#define ETH2CK_K 141
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#define ETH2PTP_K 142
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#define DCMIPP_K 143
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#define SAES_K 144
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#define DTS_K 145
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/* DDR */
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#define DDRC1 146
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#define DDRC1LP 147
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#define DDRC2 148
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#define DDRC2LP 149
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#define DDRPHYC 150
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#define DDRPHYCLP 151
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#define DDRCAPB 152
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#define DDRCAPBLP 153
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#define AXIDCG 154
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#define DDRPHYCAPB 155
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#define DDRPHYCAPBLP 156
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#define DDRPERFM 157
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#define ADC1 158
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#define ADC2 159
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#define SAI1 160
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#define SAI2 161
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#define STM32MP1_LAST_CLK 162
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/* SCMI clock identifiers */
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#define CK_SCMI_HSE 0
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#define CK_SCMI_HSI 1
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#define CK_SCMI_CSI 2
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#define CK_SCMI_LSE 3
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#define CK_SCMI_LSI 4
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#define CK_SCMI_HSE_DIV2 5
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#define CK_SCMI_PLL2_Q 6
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#define CK_SCMI_PLL2_R 7
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#define CK_SCMI_PLL3_P 8
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#define CK_SCMI_PLL3_Q 9
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#define CK_SCMI_PLL3_R 10
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#define CK_SCMI_PLL4_P 11
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#define CK_SCMI_PLL4_Q 12
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#define CK_SCMI_PLL4_R 13
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#define CK_SCMI_MPU 14
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#define CK_SCMI_AXI 15
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#define CK_SCMI_MLAHB 16
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#define CK_SCMI_CKPER 17
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#define CK_SCMI_PCLK1 18
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#define CK_SCMI_PCLK2 19
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#define CK_SCMI_PCLK3 20
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#define CK_SCMI_PCLK4 21
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#define CK_SCMI_PCLK5 22
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#define CK_SCMI_PCLK6 23
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#define CK_SCMI_CKTIMG1 24
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#define CK_SCMI_CKTIMG2 25
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#define CK_SCMI_CKTIMG3 26
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#define CK_SCMI_RTC 27
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#define CK_SCMI_RTCAPB 28
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#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */
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