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df8d759d9d
Add a generic GICV2 driver that: - parses the DT and generates the ACPI MADT subtables - implement of_xlate() and allows irq_get_by_index() to return the correct interrupt mappings Map DT interrupts to ARM GIC interrupts as follows: - Interrupt numbers ID32-ID1019 are used for SPIs - ID0-ID15 are used for SGIs - ID16-ID31 are used for PPIs TEST: Booted on QEMU raspb4 using GICV2 driver model generated MADT. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org>
90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Broadcom.
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*/
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#include <dm.h>
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#include <irq.h>
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#include <asm/gic.h>
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#include <asm/acpi_table.h>
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#include <cpu_func.h>
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#include <dm/acpi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#ifdef CONFIG_ACPIGEN
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/**
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* acpi_gicv2_fill_madt() - Fill out the body of the MADT
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*
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* Write GICD and GICR tables based on collected devicetree data.
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*
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* @dev: Device to write ACPI tables for
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* @ctx: ACPI context to write MADT sub-tables to
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* Return: 0 if OK
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*/
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static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
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{
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struct acpi_madt_gicd *gicd;
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fdt_addr_t addr;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE) {
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pr_err("%s: failed to get GICD address\n", __func__);
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return -EINVAL;
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}
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gicd = ctx->current;
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acpi_write_madt_gicd(gicd, dev_seq(dev), addr, 2);
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acpi_inc(ctx, gicd->length);
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return 0;
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}
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static struct acpi_ops gic_v2_acpi_ops = {
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.fill_madt = acpi_gicv2_fill_madt,
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};
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#endif
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static const struct udevice_id gic_v2_ids[] = {
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{ .compatible = "arm,arm11mp-gic" },
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{ .compatible = "arm,cortex-a15-gic" },
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{ .compatible = "arm,cortex-a7-gic" },
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{ .compatible = "arm,cortex-a5-gic" },
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{ .compatible = "arm,cortex-a9-gic" },
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{ .compatible = "arm,eb11mp-gic" },
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{ .compatible = "arm,gic-400" },
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{ .compatible = "arm,pl390" },
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{ .compatible = "arm,tc11mp-gic" },
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{ .compatible = "qcom,msm-8660-qgic" },
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{ .compatible = "qcom,msm-qgic2" },
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{}
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};
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static int arm_gic_v2_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
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{
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if (args->args_count != 3) {
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log_debug("Invalid args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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/* ARM Generic Interrupt Controller v1 and v2 */
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if (args->args[0] == GIC_SPI)
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irq->id = args->args[1] + 32;
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else
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irq->id = args->args[1] + 16;
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irq->flags = args->args[2];
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return 0;
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}
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static const struct irq_ops arm_gic_v2_ops = {
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.of_xlate = arm_gic_v2_of_xlate,
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};
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U_BOOT_DRIVER(arm_gic_v2) = {
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.name = "gic-v2",
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.id = UCLASS_IRQ,
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.of_match = gic_v2_ids,
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.ops = &arm_gic_v2_ops,
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ACPI_OPS_PTR(&gic_v2_acpi_ops)
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};
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