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922d4504bc
Upgrade SCFW API to 1.16 Add more APIs: sc_misc_get_button_status sc_pm_reboot sc_seco_v2x_build_info Signed-off-by: Peng Fan <peng.fan@nxp.com>
139 lines
5.1 KiB
C
139 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef SC_PM_API_H
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#define SC_PM_API_H
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#include <firmware/imx/sci/types.h>
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/* Defines for type widths */
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#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */
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#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */
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#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */
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#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */
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/* Defines for ALL parameters */
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#define SC_PM_CLK_ALL ((sc_pm_clk_t)UINT8_MAX) /* All clocks */
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/* Defines for sc_pm_power_mode_t */
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#define SC_PM_PW_MODE_OFF 0U /* Power off */
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#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
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#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
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#define SC_PM_PW_MODE_ON 3U /* Power on */
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/* Defines for sc_pm_clk_t */
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#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
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#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
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#define SC_PM_CLK_PER 2U /* Peripheral clock */
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#define SC_PM_CLK_PHY 3U /* Phy clock */
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#define SC_PM_CLK_MISC 4U /* Misc clock */
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#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
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#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
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#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
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#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
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#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
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#define SC_PM_CLK_CPU 2U /* CPU clock */
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#define SC_PM_CLK_PLL 4U /* PLL */
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#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
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/* Defines for sc_pm_clk_mode_t */
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#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
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#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
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#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
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#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
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#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
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#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
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/* Defines for sc_pm_clk_parent_t */
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#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */
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#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */
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#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */
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#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */
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#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */
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/* Defines for sc_pm_reset_type_t */
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#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
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#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
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#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
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/* Defines for sc_pm_reset_reason_t */
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#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
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#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */
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#define SC_PM_RESET_REASON_SW 2U /* Software reset */
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#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */
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#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */
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#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */
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#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */
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#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */
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#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */
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#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */
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#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */
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#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */
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#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */
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/* Defines for sc_pm_sys_if_t */
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#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
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#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
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#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
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#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
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/* Defines for sc_pm_wake_src_t */
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/* No wake source, used for self-kill */
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#define SC_PM_WAKE_SRC_NONE 0U
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/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
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#define SC_PM_WAKE_SRC_SCU 1U
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/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
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#define SC_PM_WAKE_SRC_IRQSTEER 2U
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/* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
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#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U
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/* Wakeup from GIC to wake CPU */
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#define SC_PM_WAKE_SRC_GIC 4U
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/* Types */
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/*
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* This type is used to declare a power mode. Note resources only use
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* SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
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* as system power modes.
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*/
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typedef u8 sc_pm_power_mode_t;
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/*
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* This type is used to declare a clock.
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*/
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typedef u8 sc_pm_clk_t;
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/*
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* This type is used to declare a clock mode.
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*/
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typedef u8 sc_pm_clk_mode_t;
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/*
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* This type is used to declare the clock parent.
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*/
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typedef u8 sc_pm_clk_parent_t;
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/*
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* This type is used to declare clock rates.
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*/
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typedef u32 sc_pm_clock_rate_t;
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/*
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* This type is used to declare a desired reset type.
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*/
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typedef u8 sc_pm_reset_type_t;
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/*
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* This type is used to declare a reason for a reset.
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*/
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typedef u8 sc_pm_reset_reason_t;
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/*
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* This type is used to specify a system-level interface to be power managed.
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*/
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typedef u8 sc_pm_sys_if_t;
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/*
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* This type is used to specify a wake source for CPU resources.
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*/
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typedef u8 sc_pm_wake_src_t;
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#endif /* SC_PM_API_H */
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