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The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init() during the SPL start up. On this particular system, spl_board_init() is used to reconfigure GIC clock parent to PLL2 500M, which is the configuration expected by the Linux kernel. Enable SPL_BOARD_INIT and fill in the GIC clock configuration code. Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not allow to change it. Should set the clock after PMIC setting done. Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
157 lines
4.0 KiB
C
157 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <spl.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include "lpddr4_timing.h"
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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int data_modul_imx_edm_sbc_board_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("Failed to get PMIC\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output. */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
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if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
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/* Set DVS0 to 0.85V for special case. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
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/* Set DVS1 to 0.85v for suspend. */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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/*
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
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*/
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD frequency for SoC. */
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/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
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/* DRAM Vdd1 always FPWM */
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pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
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/* DRAM Vdd2/Vddq always FPWM */
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pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
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/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
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pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
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pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
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return 0;
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}
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void spl_board_init(void)
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{
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/*
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* Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
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* allow to change it. Should set the clock after PMIC setting done.
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* Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
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* ND VDD_SOC.
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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}
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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if (boot_dev_spl == SPI_NOR_BOOT) /* SPI NOR */
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return BOOT_DEVICE_SPI;
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if (boot_dev_spl == MMC3_BOOT) /* eMMC */
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC1; /* SD */
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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int boot_device = spl_boot_device();
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spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC 8:SPI NOR */
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if (boot_device == BOOT_DEVICE_SPI) { /* SPI, eMMC, SD */
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spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
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spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
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} else if (boot_device == BOOT_DEVICE_MMC1) { /* SD, eMMC, SPI */
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spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
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spl_boot_list[2] = BOOT_DEVICE_SPI; /* SPI */
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} else { /* eMMC, SPI, SD */
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spl_boot_list[1] = BOOT_DEVICE_SPI; /* SPI */
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spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */
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}
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spl_boot_list[3] = BOOT_DEVICE_UART; /* YModem */
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spl_boot_list[4] = BOOT_DEVICE_NONE;
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}
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unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
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{
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const u32 boot_dev = spl_boot_device();
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int part;
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if (boot_dev == BOOT_DEVICE_MMC2) { /* eMMC */
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part = spl_mmc_emmc_boot_partition(mmc);
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if (part == 1 || part == 2) /* eMMC BOOT1/BOOT2 HW partitions */
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return sect - 0x40;
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}
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return sect;
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}
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static struct dram_timing_info *dram_timing_info[8] = {
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&dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */
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NULL, /* 32 Gbit x16 */
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NULL, /* 16 Gbit x32 */
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NULL, /* 16 Gbit x16 */
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NULL, /* 8 Gbit x32 */
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NULL, /* 8 Gbit x16 */
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NULL, /* INVALID */
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NULL, /* INVALID */
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};
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void board_init_f(ulong dummy)
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{
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dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
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}
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