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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
143 lines
3.3 KiB
C
143 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <config.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <cpu_func.h>
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#include <stdint.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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# define MEMSIZE_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
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#else
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/* Just use the greatest cache flush alignment requirement I'm aware of */
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# define MEMSIZE_CACHELINE_SIZE 128
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#endif
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#ifdef __PPC__
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/*
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* At least on G2 PowerPC cores, sequential accesses to non-existent
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* memory must be synchronized.
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*/
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# include <asm/io.h> /* for sync() */
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#else
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# define sync() /* nothing */
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#endif
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static void dcache_flush_invalidate(volatile long *p)
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{
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uintptr_t start, stop;
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start = ALIGN_DOWN((uintptr_t)p, MEMSIZE_CACHELINE_SIZE);
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stop = start + MEMSIZE_CACHELINE_SIZE;
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flush_dcache_range(start, stop);
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invalidate_dcache_range(start, stop);
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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long get_ram_size(long *base, long maxsize)
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{
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volatile long *addr;
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long save[BITS_PER_LONG - 1];
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long save_base;
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long cnt;
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long val;
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long size;
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int i = 0;
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int dcache_en = dcache_status();
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for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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sync();
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save[i++] = *addr;
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sync();
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*addr = ~cnt;
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if (dcache_en)
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dcache_flush_invalidate(addr);
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}
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addr = base;
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sync();
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save_base = *addr;
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sync();
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*addr = 0;
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sync();
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if (dcache_en)
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dcache_flush_invalidate(addr);
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if ((val = *addr) != 0) {
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/* Restore the original data before leaving the function. */
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sync();
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*base = save_base;
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for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
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addr = base + cnt;
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sync();
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*addr = save[--i];
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}
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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size = cnt * sizeof(long);
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/*
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* Restore the original data
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* before leaving the function.
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*/
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for (cnt <<= 1;
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cnt < maxsize / sizeof(long);
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cnt <<= 1) {
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addr = base + cnt;
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*addr = save[--i];
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}
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/* warning: don't restore save_base in this case,
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* it is already done in the loop because
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* base and base+size share the same physical memory
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* and *base is saved after *(base+size) modification
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* in first loop
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*/
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return (size);
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}
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}
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*base = save_base;
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return (maxsize);
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}
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phys_size_t __weak get_effective_memsize(void)
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{
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phys_size_t ram_size = gd->ram_size;
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#ifdef CONFIG_MPC85xx
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/*
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* Check for overflow and limit ram size to some representable value.
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* It is required that ram_base + ram_size must be representable by
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* phys_size_t type and must be aligned by direct access, therefore
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* calculate it from last 4kB sector which should work as alignment
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* on any platform.
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*/
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if (gd->ram_base + ram_size < gd->ram_base)
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ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base;
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#endif
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#ifndef CFG_MAX_MEM_MAPPED
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return ram_size;
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#else
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/* limit stack to what we can reasonable map */
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return ((ram_size > CFG_MAX_MEM_MAPPED) ?
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CFG_MAX_MEM_MAPPED : ram_size);
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#endif
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}
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