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5b66006646
Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/*
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* Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "sbc-regs.h"
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/* slower but LED works */
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#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
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#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
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#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
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#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
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/* faster but LED does not work */
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#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
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#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
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/* NOR flash needs more wait counts than SRAM */
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#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
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#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
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int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
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{
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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*/
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
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if (boot_is_swapped()) {
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/*
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* Boot Swap On: boot from external NOR/SRAM
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* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
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*
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* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
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* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
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*/
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writel(0x0000bc01, SBBASE0);
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} else {
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/*
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* Boot Swap Off: boot from mask ROM
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* 0x40000000-0x41ffffff: mask ROM
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* 0x42000000-0x43efffff: memory bank (31MB)
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* 0x43f00000-0x43ffffff: peripherals (1MB)
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*/
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writel(0x0000be01, SBBASE0); /* dummy */
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writel(0x0200be01, SBBASE1);
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}
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return 0;
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}
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