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9973e3c614
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/*
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* Copyright (C) 2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Embedded Planet EP88x boards.
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* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/*
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* SDRAM uses two Micron chips.
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* Minimal CPU frequency is 40MHz.
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*/
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static uint sdram_table[] = {
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/* Single read (offset 0x00 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
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0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Burst read (offset 0x08 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
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0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Single write (offset 0x18 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
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0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Burst write (offset 0x20 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
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0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Refresh (offset 0x30 in UPM RAM) */
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0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
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0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
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0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
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/* Exception (offset 0x3C in UPM RAM) */
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0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
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};
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int board_early_init_f (void)
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{
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vu_char *bcsr = (vu_char *)CFG_BCSR;
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bcsr[0] |= 0x0C; /* Turn the LEDs off */
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bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
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flash detection by CFI driver
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*/
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#if defined(CONFIG_8xx_CONS_SMC1)
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bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
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#endif
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#if defined(CONFIG_8xx_CONS_SCC2)
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bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
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#endif
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#ifdef CONFIG_ETHER_ON_FEC1
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bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
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#endif
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#ifdef CONFIG_ETHER_ON_FEC2
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bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
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#endif
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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long int msize;
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volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
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/* Configure SDRAM refresh */
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memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
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memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
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udelay(100);
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/* Run MRS pattern from location 0x36 */
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memctl->memc_mar = 0x88;
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memctl->memc_mcr = 0x80002236;
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udelay(100);
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memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
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memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
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memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
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msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
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memctl->memc_or1 |= ~(msize - 1);
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return msize;
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}
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int checkboard( void )
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{
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vu_char *bcsr = (vu_char *)CFG_BCSR;
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puts("Board: ");
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switch (bcsr[15]) {
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case 0xE7:
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puts("EP88xC 1.0");
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break;
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default:
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printf("unknown ID=%02X", bcsr[15]);
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}
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printf(" CPLD revision %d\n", bcsr[14]);
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return 0;
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}
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