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400558b561
- rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL - rename memsetup into lowlevel_init (function name and source files)
205 lines
5.9 KiB
ArmAsm
205 lines
5.9 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from Linux
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*
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* Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
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* (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/netarm_registers.h>
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/* some parameters for the board */
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#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
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#define FLASH_70ns_WAIT_STATES 4
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#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
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#if 1
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#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
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#else
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#define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
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#endif
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#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
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#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
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#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
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#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
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#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
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#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
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#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
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#endif
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#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
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#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
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/* setting up the memory */
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.globl lowlevel_init
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lowlevel_init:
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#if defined(CONFIG_MODNET50)
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ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
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_jump_to_high:
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/*
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* MEM Config Reg
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* ---------------------------------------------------
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*/
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ldr r0, =NETARM_MEM_MODULE_BASE
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ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
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NETARM_MEM_CFG_REFRESH_EN | \
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NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
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str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
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memsetup_cs0:
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/*
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* Base Addr / Option Reg 0 (Flash)
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* ---------------------------------------------------
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*/
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ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
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NETARM_MEM_BAR_DRAM_FP | \
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NETARM_MEM_BAR_DRAM_MUX_INT | \
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NETARM_MEM_BAR_DRAM_MUX_BAL | \
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NETARM_MEM_BAR_VALID )
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str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
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/* trust that the bus size for flash was strapped correctly */
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/* this saves the bus width in r2 and then ORs it back in */
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/* it's pretty safe assumption, otherwise it wouldn't boot */
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ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
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and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
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/* just a test: assume 32 bit flash mem */
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/* mov r2, #NETARM_MEM_OPT_32BIT */
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ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
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NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
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NETARM_MEM_OPT_BCYC_4 | \
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NETARM_MEM_OPT_BSIZE_16 | \
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NETARM_MEM_OPT_16BIT | \
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NETARM_MEM_OPT_READ_ASYNC | \
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NETARM_MEM_OPT_WRITE_ASYNC )
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orr r1, r1, r2
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str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
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memsetup_cs1:
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/*
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* Base Addr / Option Reg 1 (DRAM #1)
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* ---------------------------------------------------
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*/
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#ifdef CONFIG_NETARM_NET40_REV2
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/* we have to config SDRAM in burst mode */
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ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
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NETARM_MEM_OPT_BCYC_2 | \
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NETARM_MEM_OPT_BSIZE_16 | \
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NETARM_MEM_OPT_WAIT_STATES(0) | \
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NETARM_MEM_OPT_32BIT | \
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NETARM_MEM_OPT_READ_ASYNC | \
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NETARM_MEM_OPT_WRITE_ASYNC )
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str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
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ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
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NETARM_MEM_BAR_DRAM_SYNC | \
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NETARM_MEM_BAR_DRAM_MUX_INT | \
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NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
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NETARM_MEM_BAR_DRAM_SEL | \
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NETARM_MEM_BAR_BURST_EN | \
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NETARM_MEM_BAR_VALID )
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str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
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#else
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/* we have to config FPDRAM in burst mode with smaller burst access size */
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ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
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NETARM_MEM_OPT_BCYC_2 | \
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NETARM_MEM_OPT_BSIZE_16 | \
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NETARM_MEM_OPT_WAIT_STATES(0) | \
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NETARM_MEM_OPT_32BIT | \
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NETARM_MEM_OPT_READ_ASYNC | \
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NETARM_MEM_OPT_WRITE_ASYNC )
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str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
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ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
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NETARM_MEM_BAR_DRAM_SYNC | \
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NETARM_MEM_BAR_DRAM_MUX_INT | \
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NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
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NETARM_MEM_BAR_DRAM_SEL | \
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NETARM_MEM_BAR_BURST_EN | \
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NETARM_MEM_BAR_VALID )
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str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
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#endif /* CONFIG_NETARM_NET40_REV2 */
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memsetup_cs3:
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/*
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* Base Addr / Option Reg 3 (EEPROM, NVRAM)
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* ---------------------------------------------------
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*/
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#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
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ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
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NETARM_MEM_OPT_BCYC_3 | \
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NETARM_MEM_OPT_BSIZE_2 | \
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NETARM_MEM_OPT_WAIT_STATES(10) | \
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NETARM_MEM_OPT_8BIT | \
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NETARM_MEM_OPT_READ_ASYNC | \
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NETARM_MEM_OPT_WRITE_ASYNC )
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str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
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ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
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NETARM_MEM_BAR_DRAM_FP | \
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NETARM_MEM_BAR_DRAM_MUX_INT | \
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NETARM_MEM_BAR_DRAM_MUX_BAL | \
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NETARM_MEM_BAR_VALID )
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str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
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#else
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/* we don't need EEPROM --> no config */
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ldr r1, =( 0 )
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str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
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ldr r1, =( 0 )
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str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
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#endif
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#else
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/*
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#error "missing CONFIG_MODNET50 (see your config.h)"
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*/
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#endif /* CONFIG_MODNET50 */
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lowlevel_init_end:
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/*
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* manipulate address in lr and ip to match new
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* address space
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*/
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ldr r3, =(NETARM_MMAP_CS0_BASE)
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mov r0, lr
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add r0, r3, r0
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mov lr, r0
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mov r0, ip
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add r0, r3, r0
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mov ip, r0
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/* everything is fine now */
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mov pc, lr
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