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be059e8813
Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Taken from coreboot file of the same name
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*/
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#ifndef _X86_MP_H_
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#define _X86_MP_H_
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#include <asm/atomic.h>
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typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
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/*
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* A mp_flight_record details a sequence of calls for the APs to perform
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* along with the BSP to coordinate sequencing. Each flight record either
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* provides a barrier for each AP before calling the callback or the APs
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* are allowed to perform the callback without waiting. Regardless, each
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* record has the cpus_entered field incremented for each record. When
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* the BSP observes that the cpus_entered matches the number of APs
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* the bsp_call is called with bsp_arg and upon returning releases the
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* barrier allowing the APs to make further progress.
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*
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* Note that ap_call() and bsp_call() can be NULL. In the NULL case the
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* callback will just not be called.
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*/
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struct mp_flight_record {
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atomic_t barrier;
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atomic_t cpus_entered;
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mp_callback_t ap_call;
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void *ap_arg;
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mp_callback_t bsp_call;
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void *bsp_arg;
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} __attribute__((aligned(ARCH_DMA_MINALIGN)));
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#define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
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{ \
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.barrier = ATOMIC_INIT(barrier_), \
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.cpus_entered = ATOMIC_INIT(0), \
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.ap_call = ap_func_, \
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.ap_arg = ap_arg_, \
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.bsp_call = bsp_func_, \
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.bsp_arg = bsp_arg_, \
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}
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#define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
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MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
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#define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
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MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
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/*
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* The mp_params structure provides the arguments to the mp subsystem
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* for bringing up APs.
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*
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* At present this is overkill for U-Boot, but it may make it easier to add
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* SMM support.
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*/
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struct mp_params {
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int parallel_microcode_load;
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const void *microcode_pointer;
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/* Flight plan for APs and BSP */
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struct mp_flight_record *flight_plan;
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int num_records;
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};
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/*
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* mp_init() will set up the SIPI vector and bring up the APs according to
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* mp_params. Each flight record will be executed according to the plan. Note
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* that the MP infrastructure uses SMM default area without saving it. It's
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* up to the chipset or mainboard to either e820 reserve this area or save this
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* region prior to calling mp_init() and restoring it after mp_init returns.
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*
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* At the time mp_init() is called the MTRR MSRs are mirrored into APs then
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* caching is enabled before running the flight plan.
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*
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* The MP init has the following properties:
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* 1. APs are brought up in parallel.
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* 2. The ordering of cpu number and APIC ids is not deterministic.
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* Therefore, one cannot rely on this property or the order of devices in
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* the device tree unless the chipset or mainboard know the APIC ids
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* a priori.
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*
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* mp_init() returns < 0 on error, 0 on success.
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*/
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int mp_init(struct mp_params *params);
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/* Probes the CPU device */
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int mp_init_cpu(struct udevice *cpu, void *unused);
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/* Set up additional CPUs */
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int x86_mp_init(void);
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#endif /* _X86_MP_H_ */
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