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7fbeb6422d
The rsk7264 (also know as rsk2+sh7264) is an SH2A based board with 64MB NAND flash and 64MB SDRAM. It is very similar to the rsk7203 board. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
106 lines
2.0 KiB
C
106 lines
2.0 KiB
C
/*
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* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#define STBCR4 0xFFFE040C
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#define cmt_clock_enable() do {\
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writeb(readb(STBCR4) & ~0x04, STBCR4);\
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} while (0)
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#define scif0_enable() do {\
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writeb(readb(STBCR4) & ~0x80, STBCR4);\
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} while (0)
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#define scif3_enable() do {\
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writeb(readb(STBCR4) & ~0x10, STBCR4);\
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} while (0)
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int checkcpu(void)
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{
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#if defined(CONFIG_SH2A)
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puts("CPU: SH2A\n");
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#else
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puts("CPU: SH2\n");
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#endif
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return 0;
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}
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int cpu_init(void)
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{
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/* SCIF enable */
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#if defined(CONFIG_CONS_SCIF3)
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scif3_enable();
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#else
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scif0_enable();
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#endif
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/* CMT clock enable */
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cmt_clock_enable() ;
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return 0;
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}
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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return 0;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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reset_cpu(0);
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return 0;
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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