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9112ef8d89
This driver supports SPI on Tegra2, running at 48MHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* NVIDIA Tegra2 SPI-FLASH controller
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*
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* Copyright 2010-2011 NVIDIA Corporation
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA2_SPI_H_
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#define _TEGRA2_SPI_H_
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#include <asm/types.h>
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struct spi_tegra {
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u32 command; /* SPI_COMMAND_0 register */
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u32 status; /* SPI_STATUS_0 register */
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u32 rx_cmp; /* SPI_RX_CMP_0 register */
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u32 dma_ctl; /* SPI_DMA_CTL_0 register */
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u32 tx_fifo; /* SPI_TX_FIFO_0 register */
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u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
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u32 rx_fifo; /* SPI_RX_FIFO_0 register */
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};
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#define SPI_CMD_GO (1 << 30)
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#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
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#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
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#define SPI_CMD_CK_SDA (1 << 21)
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#define SPI_CMD_ACTIVE_SDA_SHIFT 18
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#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
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#define SPI_CMD_CS_POL (1 << 16)
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#define SPI_CMD_TXEN (1 << 15)
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#define SPI_CMD_RXEN (1 << 14)
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#define SPI_CMD_CS_VAL (1 << 13)
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#define SPI_CMD_CS_SOFT (1 << 12)
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#define SPI_CMD_CS_DELAY (1 << 9)
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#define SPI_CMD_CS3_EN (1 << 8)
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#define SPI_CMD_CS2_EN (1 << 7)
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#define SPI_CMD_CS1_EN (1 << 6)
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#define SPI_CMD_CS0_EN (1 << 5)
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#define SPI_CMD_BIT_LENGTH (1 << 4)
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#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
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#define SPI_STAT_BSY (1 << 31)
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#define SPI_STAT_RDY (1 << 30)
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#define SPI_STAT_RXF_FLUSH (1 << 29)
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#define SPI_STAT_TXF_FLUSH (1 << 28)
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#define SPI_STAT_RXF_UNR (1 << 27)
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#define SPI_STAT_TXF_OVF (1 << 26)
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#define SPI_STAT_RXF_EMPTY (1 << 25)
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#define SPI_STAT_RXF_FULL (1 << 24)
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#define SPI_STAT_TXF_EMPTY (1 << 23)
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#define SPI_STAT_TXF_FULL (1 << 22)
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#define SPI_STAT_SEL_TXRX_N (1 << 16)
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#define SPI_STAT_CUR_BLKCNT (1 << 15)
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#define SPI_TIMEOUT 1000
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#define TEGRA2_SPI_MAX_FREQ 52000000
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#endif /* _TEGRA2_SPI_H_ */
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