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ca93e32139
RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
266 lines
7.6 KiB
C
266 lines
7.6 KiB
C
/*
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* Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SDRAM_RK3328_H
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#define _ASM_ARCH_SDRAM_RK3328_H
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#include <asm/arch-rockchip/sdram_common.h>
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#include <asm/arch-rockchip/sdram_pctl_px30.h>
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#include <asm/arch-rockchip/sdram_phy_px30.h>
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#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
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#define SR_IDLE 93
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#define PD_IDLE 13
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#define SDRAM_ADDR 0x00000000
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/* noc registers define */
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#define DDRCONF 0x8
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#define DDRTIMING 0xc
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#define DDRMODE 0x10
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#define READLATENCY 0x14
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#define AGING0 0x18
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#define AGING1 0x1c
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#define AGING2 0x20
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#define AGING3 0x24
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#define AGING4 0x28
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#define AGING5 0x2c
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#define ACTIVATE 0x38
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#define DEVTODEV 0x3c
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#define DDR4TIMING 0x40
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/* DDR GRF */
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#define DDR_GRF_CON(n) (0 + (n) * 4)
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#define DDR_GRF_STATUS_BASE (0X100)
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#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
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/* CRU_SOFTRESET_CON5 */
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#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15))
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#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14))
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#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13))
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#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12))
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#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11))
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#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
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#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8))
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#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7))
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/* CRU_SOFTRESET_CON9 */
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#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
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/* CRU register */
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#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
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#define CRU_MODE (0x80)
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#define CRU_GLB_CNT_TH (0x90)
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#define CRU_CLKSEL_CON_BASE 0x100
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
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#define CRU_CLKGATE_CON_BASE 0x200
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#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
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#define CRU_CLKSFTRST_CON_BASE 0x300
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#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
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/* CRU_PLL_CON0 */
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#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
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#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
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#define FBDIV(n) ((0xFFF << 16) | (n))
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/* CRU_PLL_CON1 */
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#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
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#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
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#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
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#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
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#define LOCK(n) (((n) >> 10) & 0x1)
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#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
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#define REFDIV(n) ((0x3F << 16) | (n))
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u16 ddr_cfg_2_rbc[] = {
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/*
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* [5:4] row(13+n)
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* [3] cs(0:0 cs, 1:2 cs)
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* [2] bank(0:0bank,1:8bank)
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* [1:0] col(11+n)
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*/
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/* row, cs, bank, col */
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((3 << 4) | (0 << 3) | (1 << 2) | 0),
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((3 << 4) | (0 << 3) | (1 << 2) | 1),
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((2 << 4) | (0 << 3) | (1 << 2) | 2),
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((3 << 4) | (0 << 3) | (1 << 2) | 2),
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((2 << 4) | (0 << 3) | (1 << 2) | 3),
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((3 << 4) | (1 << 3) | (1 << 2) | 0),
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((3 << 4) | (1 << 3) | (1 << 2) | 1),
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((2 << 4) | (1 << 3) | (1 << 2) | 2),
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((3 << 4) | (0 << 3) | (0 << 2) | 1),
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((2 << 4) | (0 << 3) | (1 << 2) | 1),
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};
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u16 ddr4_cfg_2_rbc[] = {
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/***************************
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* [6] cs 0:0cs 1:2 cs
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* [5:3] row(13+n)
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* [2] cs(0:0 cs, 1:2 cs)
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* [1] bw 0: 16bit 1:32bit
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* [0] diebw 0:8bit 1:16bit
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***************************/
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/* cs, row, cs, bw, diebw */
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((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
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((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
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((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
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((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
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((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
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((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
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((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
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((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
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((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
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((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
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((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
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};
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u32 addrmap[21][9] = {
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/* map0 map1 map2 map3 map4 map5 map6 map7 map8 */
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{22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
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0x06060606, 0x00000f0f, 0x3f3f},
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{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f0f, 0x3f3f},
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{23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
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0x0f080808, 0x00000f0f, 0x3f3f},
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{24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
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0x08080808, 0x00000f0f, 0x3f3f},
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{24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
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0x0f090909, 0x00000f0f, 0x3f3f},
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{6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f0f, 0x3f3f},
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{7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
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0x08080808, 0x00000f0f, 0x3f3f},
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{8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
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0x0f090909, 0x00000f0f, 0x3f3f},
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{22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
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0x06060606, 0x00000f0f, 0x3f3f},
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{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
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0x0f070707, 0x00000f0f, 0x3f3f},
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{24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
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0x08080808, 0x00000f0f, 0x0801},
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{23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
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0x0f080808, 0x00000f0f, 0x0801},
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{24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f07, 0x0700},
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{23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f0f, 0x0700},
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{24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f07, 0x3f01},
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{23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f0f, 0x3f01},
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{24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
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0x06060606, 0x00000f06, 0x3f00},
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{8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
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0x0f090909, 0x00000f0f, 0x0801},
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{7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
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0x08080808, 0x00000f0f, 0x0700},
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{7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
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0x08080808, 0x00000f0f, 0x3f01},
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{6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
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0x07070707, 0x00000f07, 0x3f00}
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};
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struct rk3328_ddr_grf_regs {
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u32 ddr_grf_con[4];
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u32 reserved[(0x100 - 0x10) / 4];
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u32 ddr_grf_status[11];
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};
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union noc_ddrtiming {
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u32 d32;
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struct {
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unsigned acttoact:6;
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unsigned rdtomiss:6;
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unsigned wrtomiss:6;
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unsigned burstlen:3;
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unsigned rdtowr:5;
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unsigned wrtord:5;
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unsigned bwratio:1;
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} b;
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};
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union noc_activate {
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u32 d32;
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struct {
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unsigned rrd:4;
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unsigned faw:6;
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unsigned fawbank:1;
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unsigned reserved1:21;
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} b;
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};
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union noc_devtodev {
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u32 d32;
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struct {
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unsigned busrdtord:2;
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unsigned busrdtowr:2;
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unsigned buswrtord:2;
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unsigned reserved2:26;
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} b;
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};
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union noc_ddr4timing {
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u32 d32;
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struct {
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unsigned ccdl:3;
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unsigned wrtordl:5;
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unsigned rrdl:4;
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unsigned reserved2:20;
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} b;
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};
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union noc_ddrmode {
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u32 d32;
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struct {
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unsigned autoprecharge:1;
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unsigned bwratioextended:1;
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unsigned reserved3:30;
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} b;
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};
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struct msch_regs {
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u32 coreid;
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u32 revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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u32 aging0;
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u32 aging1;
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u32 aging2;
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u32 aging3;
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u32 aging4;
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u32 aging5;
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u32 reserved[2];
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u32 activate;
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u32 devtodev;
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u32 ddr4_timing;
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};
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struct sdram_msch_timings {
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union noc_ddrtiming ddrtiming;
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union noc_ddrmode ddrmode;
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u32 readlatency;
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union noc_activate activate;
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union noc_devtodev devtodev;
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union noc_ddr4timing ddr4timing;
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u32 agingx0;
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};
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struct rk3328_sdram_channel {
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struct sdram_cap_info cap_info;
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struct sdram_msch_timings noc_timings;
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};
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struct rk3328_sdram_params {
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struct rk3328_sdram_channel ch;
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struct sdram_base_params base;
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struct ddr_pctl_regs pctl_regs;
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struct ddr_phy_regs phy_regs;
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struct ddr_phy_skew skew;
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};
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#endif
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