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10552377d4
Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
58 lines
1.2 KiB
C
58 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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* Copyright 2019 Google LLC
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*/
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#ifndef _ASM_ARCH_PM_H
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#define _ASM_ARCH_PM_H
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#include <power/acpi_pmc.h>
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#define PMC_GPE_SW_31_0 0
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#define PMC_GPE_SW_63_32 1
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#define PMC_GPE_NW_31_0 3
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#define PMC_GPE_NW_63_32 4
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#define PMC_GPE_NW_95_64 5
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#define PMC_GPE_N_31_0 6
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#define PMC_GPE_N_63_32 7
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#define PMC_GPE_W_31_0 9
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#define IRQ_REG 0x106c
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#define SCI_IRQ_SHIFT 24
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#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT)
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#define SCIS_IRQ9 9
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#define SCIS_IRQ10 10
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#define SCIS_IRQ11 11
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#define SCIS_IRQ20 20
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#define SCIS_IRQ21 21
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#define SCIS_IRQ22 22
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#define SCIS_IRQ23 23
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/* P-state configuration */
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#define PSS_MAX_ENTRIES 8
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#define PSS_RATIO_STEP 2
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#define PSS_LATENCY_TRANSITION 10
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#define PSS_LATENCY_BUSMASTER 10
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#ifndef __ASSEMBLY__
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/* Track power state from reset to log events */
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struct __packed chipset_power_state {
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u16 pm1_sts;
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u16 pm1_en;
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u32 pm1_cnt;
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u32 gpe0_sts[GPE0_REG_MAX];
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u32 gpe0_en[GPE0_REG_MAX];
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u16 tco1_sts;
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u16 tco2_sts;
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u32 prsts;
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u32 gen_pmcon1;
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u32 gen_pmcon2;
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u32 gen_pmcon3;
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u32 prev_sleep_state;
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};
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#endif /* !__ASSEMBLY__ */
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#endif
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