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7cb50cd477
There exists a situation of the mediatek pinctrl driver that may return
wrong pin function value for the pinmux driver:
- All pin function arrays are defined without const
- Some pin function arrays contain all-zero value, e.g.:
static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
- These arrays will be put into .bss section during compilation
- .bss section has no "a" attribute and does not exist in the final binary
file after objcopy.
- FDT binary blob is appended to the u-boot binary, which occupies the
.bss section.
- During board_f stage, .bss has not been initialized, and contains the
data of FDT, which is not full-zero data.
- pinctrl driver is initialized in board_f stage, and it will get wrong
data if another driver is going to set default pinctrl.
Since pinmux information and soc data are only meant to be read-only, thus
should be declared as const. This will force all pinctrl data being put
into .rodata section. Since .rodata has "a" attribute, even the all-zero
data will be allocated and filled with correct value in to u-boot binary.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
266 lines
7.0 KiB
C
266 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#ifndef __PINCTRL_MEDIATEK_H__
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#define __PINCTRL_MEDIATEK_H__
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#define MTK_PINCTRL_V0 0x0
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#define MTK_PINCTRL_V1 0x1
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#define BASE_CALC_NONE 0
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#define MAX_BASE_CALC 10
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#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
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#define MTK_PIN(_number, _name, _drv_n) \
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MTK_TYPED_PIN(_number, _name, _drv_n, IO_TYPE_DEFAULT)
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#define MTK_TYPED_PIN(_number, _name, _drv_n, _io_n) { \
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.number = _number, \
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.name = _name, \
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.drv_n = _drv_n, \
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.io_n = _io_n, \
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}
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#define PINCTRL_PIN_GROUP(name, id) \
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{ \
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name, \
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id##_pins, \
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ARRAY_SIZE(id##_pins), \
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id##_funcs, \
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}
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#define PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
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_s_bit, _x_bits, _sz_reg, _fixed) { \
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.s_pin = _s_pin, \
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.e_pin = _e_pin, \
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.i_base = _i_base, \
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.s_addr = _s_addr, \
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.x_addrs = _x_addrs, \
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.s_bit = _s_bit, \
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.x_bits = _x_bits, \
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.sz_reg = _sz_reg, \
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.fixed = _fixed, \
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}
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#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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_x_bits, _sz_reg, _fixed) \
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PIN_FIELD_BASE_CALC(_s_pin, _e_pin, BASE_CALC_NONE, _s_addr, \
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_x_addrs, _s_bit, _x_bits, _sz_reg, _fixed)
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/* List these attributes which could be modified for the pin */
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enum {
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PINCTRL_PIN_REG_MODE,
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PINCTRL_PIN_REG_DIR,
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PINCTRL_PIN_REG_DI,
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PINCTRL_PIN_REG_DO,
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PINCTRL_PIN_REG_SMT,
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PINCTRL_PIN_REG_PD,
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PINCTRL_PIN_REG_PU,
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PINCTRL_PIN_REG_E4,
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PINCTRL_PIN_REG_E8,
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PINCTRL_PIN_REG_IES,
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PINCTRL_PIN_REG_PULLEN,
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PINCTRL_PIN_REG_PULLSEL,
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PINCTRL_PIN_REG_DRV,
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PINCTRL_PIN_REG_PUPD,
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PINCTRL_PIN_REG_R0,
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PINCTRL_PIN_REG_R1,
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PINCTRL_PIN_REG_MAX,
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};
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/* Group the pins by the driving current */
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enum {
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DRV_FIXED,
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DRV_GRP0,
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DRV_GRP1,
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DRV_GRP2,
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DRV_GRP3,
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DRV_GRP4,
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};
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/* Group the pins by the io type */
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enum {
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IO_TYPE_DEFAULT,
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IO_TYPE_GRP0,
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IO_TYPE_GRP1,
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IO_TYPE_GRP2,
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IO_TYPE_GRP3,
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IO_TYPE_GRP4,
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IO_TYPE_GRP5,
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IO_TYPE_GRP6,
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};
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/**
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* struct mtk_pin_field - the structure that holds the information of the field
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* used to describe the attribute for the pin
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* @index: the index pointing to the entry in base address list
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* @offset: the register offset relative to the base address
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* @mask: the mask used to filter out the field from the register
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* @bitpos: the start bit relative to the register
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* @next: the indication that the field would be extended to the
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next register
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*/
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struct mtk_pin_field {
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u8 index;
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u32 offset;
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u32 mask;
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u8 bitpos;
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u8 next;
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};
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/**
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* struct mtk_pin_field_calc - the structure that holds the range providing
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* the guide used to look up the relevant field
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* @s_pin: the start pin within the range
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* @e_pin: the end pin within the range
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* @i_base: the index pointing to the entry in base address list
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* @s_addr: the start address for the range
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* @x_addrs: the address distance between two consecutive registers
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* within the range
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* @s_bit: the start bit for the first register within the range
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* @x_bits: the bit distance between two consecutive pins within
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* the range
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* @sz_reg: the size of bits in a register
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* @fixed: the consecutive pins share the same bits with the 1st
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* pin
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*/
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struct mtk_pin_field_calc {
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u16 s_pin;
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u16 e_pin;
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u8 i_base;
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u32 s_addr;
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u8 x_addrs;
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u8 s_bit;
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u8 x_bits;
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u8 sz_reg;
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u8 fixed;
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};
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/**
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* struct mtk_pin_reg_calc - the structure that holds all ranges used to
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* determine which register the pin would make use of
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* for certain pin attribute.
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* @range: the start address for the range
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* @nranges: the number of items in the range
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*/
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struct mtk_pin_reg_calc {
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const struct mtk_pin_field_calc *range;
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unsigned int nranges;
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};
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/**
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* struct mtk_pin_desc - the structure that providing information
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* for each pin of chips
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* @number: unique pin number from the global pin number space
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* @name: name for this pin
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* @drv_n: the index with the driving group
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* @io_n: the index with the io type
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*/
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struct mtk_pin_desc {
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unsigned int number;
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const char *name;
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u8 drv_n;
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u8 io_n;
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};
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/**
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* struct mtk_group_desc - generic pin group descriptor
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* @name: name of the pin group
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* @pins: array of pins that belong to the group
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* @num_pins: number of pins in the group
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* @data: pin controller driver specific data
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*/
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struct mtk_group_desc {
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const char *name;
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const int *pins;
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int num_pins;
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const void *data;
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};
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/**
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* struct mtk_function_desc - generic function descriptor
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* @name: name of the function
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* @group_names: array of pin group names
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* @num_group_names: number of pin group names
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*/
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struct mtk_function_desc {
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const char *name;
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const char * const *group_names;
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int num_group_names;
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};
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/**
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* struct mtk_io_type_desc - io class descriptor for specific pins
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* @name: name of the io class
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*/
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struct mtk_io_type_desc {
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const char *name;
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#if CONFIG_IS_ENABLED(PINCONF)
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/* Specific pinconfig operations */
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int (*bias_set)(struct udevice *dev, u32 pin, bool disable,
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bool pullup, u32 val);
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int (*drive_set)(struct udevice *dev, u32 pin, u32 arg);
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int (*input_enable)(struct udevice *dev, u32 pin, u32 arg);
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#endif
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};
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/* struct mtk_pin_soc - the structure that holds SoC-specific data */
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struct mtk_pinctrl_soc {
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const char *name;
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const struct mtk_pin_reg_calc *reg_cal;
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const struct mtk_pin_desc *pins;
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int npins;
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const struct mtk_group_desc *grps;
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int ngrps;
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const struct mtk_function_desc *funcs;
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int nfuncs;
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const struct mtk_io_type_desc *io_type;
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u8 ntype;
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int gpio_mode;
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const char * const *base_names;
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unsigned int nbase_names;
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int rev;
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int base_calc;
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};
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/**
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* struct mtk_pinctrl_priv - private data for MTK pinctrl driver
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*
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* @base: base address of the pinctrl device
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* @soc: SoC specific data
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*/
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struct mtk_pinctrl_priv {
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void __iomem *base[MAX_BASE_CALC];
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const struct mtk_pinctrl_soc *soc;
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};
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extern const struct pinctrl_ops mtk_pinctrl_ops;
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/* A common read-modify-write helper for MediaTek chips */
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void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
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void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
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int mtk_pinctrl_common_probe(struct udevice *dev,
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const struct mtk_pinctrl_soc *soc);
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#if CONFIG_IS_ENABLED(PINCONF)
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int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable,
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bool pullup, u32 val);
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int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
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bool disable, bool pullup, u32 val);
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int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
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bool pullup, u32 val);
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int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
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bool pullup, u32 val);
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int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
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bool pullup, u32 val);
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int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg);
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int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg);
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int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg);
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#endif
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#endif /* __PINCTRL_MEDIATEK_H__ */
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