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137 lines
4.3 KiB
Plaintext
137 lines
4.3 KiB
Plaintext
AMCC Ebony Board
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Last Update: September 12, 2002
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=======================================================================
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This file contains some handy info regarding U-Boot and the AMCC
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Ebony evalutation board. See the README.ppc440 for additional
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information.
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SWITCH SETTINGS & JUMPERS
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==========================
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Here's what I've been using successfully. If you feel inclined to
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change things ... please read the docs!
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DIPSW U46 U80
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------------------------
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SW 1 off on
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SW 2 on on
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SW 3 on on
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SW 4 off on
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SW 5 on off
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SW 6 on on
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SW 7 on off
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SW 8 on off
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J41: strapped
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J42: open
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All others are factory default.
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I2C iprobe
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=====================
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The i2c utilities have been tested on both Rev B. and Rev C. and
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look good. The CFG_I2C_NOPROBES macro is defined to prevent
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probing the CDCV850 clock controller at address 0x69 (since reading
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it causes the i2c implementation to misbehave. The output of
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iprobe should look like this (assuming you are only using a single
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SO-DIMM:
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=> iprobe
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Valid chip addresses: 50 53 54
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Excluded chip addresses: 69
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GETTING OUT OF I2C TROUBLE
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===========================
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If you're like me ... you may have screwed up your bootstrap serial
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eeprom ... or worse, your SPD eeprom when experimenting with the
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i2c commands. If so, here are some ideas on how to get out of
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trouble:
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Serial bootstrap eeprom corruption:
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-----------------------------------
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Power down the board and set the following straps:
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J41 - open
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J42 - strapped
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This will select the default sys0 and sys1 settings (the serial
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eeproms are not used). Then power up the board and fix the serial
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eeprom using the imm command. Here are the values I currently
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use:
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=> imd 50 0 10
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0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
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=> imd 54 0 10
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0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
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Once you have the eeproms set correctly change the
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J41/J42 straps as you desire.
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SPD eeprom corruption:
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------------------------
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I've corrupted the SPD eeprom several times ... perhaps too much coffee
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and not enough presence of mind ;-). By default, the ebony code uses
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the SPD to initialize the DDR SDRAM control registers. So if the SPD
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eeprom is corrupted, U-Boot will never get into ram. Here's how I got
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out of this situation:
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0. First, _before_ playing with the i2c utilities, do an iprobe, then
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use imd to capture the various device contents to a file. Some day
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you may be glad you did this ... trust me :-). Otherwise try the
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following:
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1. In the include/configs/EBONY.h file find the line that defines
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the CONFIG_SPD_EEPROM macro and undefine it. E.g:
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#undef CONFIG_SPD_EEPROM
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This will make the code use default SDRAM control register
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settings without using the SPD eeprom.
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2. Rebuild U-Boot
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3. Load the new U-Boot image and reboot ebony.
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4. Repair the SPD eeprom using the imm command. Here's the eeprom
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contents that work with the default SO-DIMM that comes with the
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ebony board (micron 8VDDT164AG-265A1). Note: these are probably
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_not_ the factory settings ... but they work.
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=> imd 53 0 10 80
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0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
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0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
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0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
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0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
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0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
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0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
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0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
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0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
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PCI DOUBLE-ENUMERATION WOES
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===========================
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If you're not using PCI-X cards and are simply using 32-bit and/or
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33 MHz cards via extenders and the like, you may notice that the
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initial pci scan reports various devices twice ... and configuration
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does not succeed (one or more devices are enumerated twice). To correct
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this we replaced the 2K ohm resistor on the IDSEL line(s) with a
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22 ohm resistor and the problem went away. This change hasn't broken
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anything yet -- use at your own risk.
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We never tested anything other than 33 MHz/32-bit cards. If you have
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the chance to do this, please let me know how things turn out :-)
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Regards,
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--Scott
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<smcnutt@artesyncp.com>
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