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https://github.com/smaeul/u-boot.git
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4a5517094d
- add support for Altera Nios-32 CPU
- add support for Nios Cyclone Development Kit (DK-1C20)
* Patch by Steven Scholz, 29 Sep 2003:
- A second parameter for bootm overwrites the load address for
"Standalone Application" images.
- bootm sets environment variable "filesize" to the resulting
(uncompressed) data length for "Standalone Application" images
when autostart is set to "no". Now you can do something like
if bootm $fpgadata $some_free_ram ; then
fpga load 0 $some_free_ram $filesize
fi
* Patch by Denis Peter, 25 Sept 2003:
add support for the MIP405 Rev. C board
78 lines
2.9 KiB
C
78 lines
2.9 KiB
C
/*
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* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __NIOS_H__
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#define __NIOS_H__
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/*------------------------------------------------------------------------
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* Control registers -- use with wrctl() & rdctl()
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*----------------------------------------------------------------------*/
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#define CTL_STATUS 0x00 /* Processor status */
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#define CTL_ISTATUS 0x01 /* Saved status (exception) */
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#define CTL_WVALID 0x02 /* Valid window limit */
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#define CTL_ICACHE 0x05 /* I-cache line-invalidate */
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#define CTL_CPU_ID 0x06 /* CPU version id */
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#define CTL_DCACHE 0x07 /* D-cache line-invalidate */
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#define CTL_CLR_IE 0x08 /* Interrupt clear (disable) */
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#define CTL_SET_IE 0x09 /* Interrupt set (enable) */
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/*------------------------------------------------------------------------
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* Access to control regs
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*----------------------------------------------------------------------*/
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#define _str_(s) #s
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#define rdctl(reg)\
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({unsigned int val;\
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asm volatile( "pfx " _str_(reg) "\n\t rdctl %0"\
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: "=r" (val) ); val;})
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#define wrctl(reg,val)\
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asm volatile( "pfx " _str_(reg) "\n\t wrctl %0 \n\t nop"\
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: : "r" (val))
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/*------------------------------------------------------------------------
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* Control reg bit masks
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*----------------------------------------------------------------------*/
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#define STATUS_DC (1<<17) /* Data cache enable */
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#define STATUS_IC (1<<16) /* Instruction cache enable */
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#define STATUS_IE (1<<15) /* Interrupt enable */
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#define STATUS_IPRI (0x3f<<9) /* Interrupt priority */
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#define STATUS_CWP (0x1f<<4) /* Current window pointer */
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#define STATUS_N (1<<3) /* Condition code: negative */
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#define STATUS_V (1<<2) /* Condition code: overflow */
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#define STATUS_Z (1<<1) /* Condition code: zero */
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#define STATUS_C (1<<0) /* Condition code: carry/borrow */
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static inline unsigned ipri( unsigned prio )
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{
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unsigned tmp;
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unsigned status = rdctl(CTL_STATUS);
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prio = (prio << 9) & STATUS_IPRI;
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tmp = (status & ~STATUS_IPRI) | prio;
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wrctl(CTL_STATUS,tmp);
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return( (status & STATUS_IPRI) >> 9);
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}
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#endif /* __NIOS_H__ */
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