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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
32 lines
811 B
C
32 lines
811 B
C
/*
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* Copyright (C) 2008-2013 Tensilica Inc.
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_ADDRSPACE_H
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#define _XTENSA_ADDRSPACE_H
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#include <asm/arch/core.h>
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/*
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* MMU Memory Map
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*
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* noMMU and v3 MMU have identity mapped address space on reset.
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* V2 MMU:
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* IO (uncached) f0000000..ffffffff -> f000000
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* IO (cached) e0000000..efffffff -> f000000
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* MEM (uncached) d8000000..dfffffff -> 0000000
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* MEM (cached) d0000000..d7ffffff -> 0000000
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*
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* The actual location of memory and IO is the board property.
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*/
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#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x))
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#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x))
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#define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
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XCHAL_VECBASE_RESET_PADDR)
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#endif /* _XTENSA_ADDRSPACE_H */
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