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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
26 lines
596 B
C
26 lines
596 B
C
/*
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* Copyright (C) 2009 Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_CACHE_H
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#define _XTENSA_CACHE_H
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#include <asm/arch/core.h>
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#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE
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#ifndef __ASSEMBLY__
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void __flush_dcache_all(void);
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void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size);
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void __invalidate_dcache_all(void);
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void __invalidate_dcache_range(unsigned long addr, unsigned long size);
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void __invalidate_icache_all(void);
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void __invalidate_icache_range(unsigned long addr, unsigned long size);
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#endif
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#endif /* _XTENSA_CACHE_H */
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