mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-25 18:18:19 +01:00
b4052d55ad
Synchronise device tree with linux v5.19-rc5. Please note that this also means that instead of the previous "generic" U-Boot specific carrier board agnostic device tree we are now using the regular one for the Colibri Evaluation (carrier) board V3 (e.g. vf610-colibri-eval-v3.dtb rather than the previous vf610-colibri.dtb). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
203 lines
6.1 KiB
C
203 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#ifndef __DT_BINDINGS_CLOCK_VF610_H
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#define __DT_BINDINGS_CLOCK_VF610_H
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#define VF610_CLK_DUMMY 0
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#define VF610_CLK_SIRC_128K 1
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#define VF610_CLK_SIRC_32K 2
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#define VF610_CLK_FIRC 3
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#define VF610_CLK_SXOSC 4
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#define VF610_CLK_FXOSC 5
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#define VF610_CLK_FXOSC_HALF 6
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#define VF610_CLK_SLOW_CLK_SEL 7
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#define VF610_CLK_FASK_CLK_SEL 8
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#define VF610_CLK_AUDIO_EXT 9
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#define VF610_CLK_ENET_EXT 10
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#define VF610_CLK_PLL1_SYS 11
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#define VF610_CLK_PLL1_PFD1 12
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#define VF610_CLK_PLL1_PFD2 13
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#define VF610_CLK_PLL1_PFD3 14
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#define VF610_CLK_PLL1_PFD4 15
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#define VF610_CLK_PLL2_BUS 16
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#define VF610_CLK_PLL2_PFD1 17
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#define VF610_CLK_PLL2_PFD2 18
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#define VF610_CLK_PLL2_PFD3 19
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#define VF610_CLK_PLL2_PFD4 20
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#define VF610_CLK_PLL3_USB_OTG 21
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#define VF610_CLK_PLL3_PFD1 22
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#define VF610_CLK_PLL3_PFD2 23
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#define VF610_CLK_PLL3_PFD3 24
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#define VF610_CLK_PLL3_PFD4 25
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#define VF610_CLK_PLL4_AUDIO 26
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#define VF610_CLK_PLL5_ENET 27
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#define VF610_CLK_PLL6_VIDEO 28
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#define VF610_CLK_PLL3_MAIN_DIV 29
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#define VF610_CLK_PLL4_MAIN_DIV 30
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#define VF610_CLK_PLL6_MAIN_DIV 31
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#define VF610_CLK_PLL1_PFD_SEL 32
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#define VF610_CLK_PLL2_PFD_SEL 33
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#define VF610_CLK_SYS_SEL 34
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#define VF610_CLK_DDR_SEL 35
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#define VF610_CLK_SYS_BUS 36
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#define VF610_CLK_PLATFORM_BUS 37
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#define VF610_CLK_IPG_BUS 38
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#define VF610_CLK_UART0 39
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#define VF610_CLK_UART1 40
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#define VF610_CLK_UART2 41
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#define VF610_CLK_UART3 42
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#define VF610_CLK_UART4 43
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#define VF610_CLK_UART5 44
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#define VF610_CLK_PIT 45
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#define VF610_CLK_I2C0 46
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#define VF610_CLK_I2C1 47
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#define VF610_CLK_I2C2 48
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#define VF610_CLK_I2C3 49
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#define VF610_CLK_FTM0_EXT_SEL 50
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#define VF610_CLK_FTM0_FIX_SEL 51
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#define VF610_CLK_FTM0_EXT_FIX_EN 52
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#define VF610_CLK_FTM1_EXT_SEL 53
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#define VF610_CLK_FTM1_FIX_SEL 54
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#define VF610_CLK_FTM1_EXT_FIX_EN 55
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#define VF610_CLK_FTM2_EXT_SEL 56
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#define VF610_CLK_FTM2_FIX_SEL 57
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#define VF610_CLK_FTM2_EXT_FIX_EN 58
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#define VF610_CLK_FTM3_EXT_SEL 59
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#define VF610_CLK_FTM3_FIX_SEL 60
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#define VF610_CLK_FTM3_EXT_FIX_EN 61
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#define VF610_CLK_FTM0 62
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#define VF610_CLK_FTM1 63
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#define VF610_CLK_FTM2 64
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#define VF610_CLK_FTM3 65
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#define VF610_CLK_ENET_50M 66
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#define VF610_CLK_ENET_25M 67
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#define VF610_CLK_ENET_SEL 68
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#define VF610_CLK_ENET 69
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#define VF610_CLK_ENET_TS_SEL 70
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#define VF610_CLK_ENET_TS 71
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#define VF610_CLK_DSPI0 72
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#define VF610_CLK_DSPI1 73
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#define VF610_CLK_DSPI2 74
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#define VF610_CLK_DSPI3 75
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#define VF610_CLK_WDT 76
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#define VF610_CLK_ESDHC0_SEL 77
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#define VF610_CLK_ESDHC0_EN 78
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#define VF610_CLK_ESDHC0_DIV 79
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#define VF610_CLK_ESDHC0 80
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#define VF610_CLK_ESDHC1_SEL 81
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#define VF610_CLK_ESDHC1_EN 82
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#define VF610_CLK_ESDHC1_DIV 83
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#define VF610_CLK_ESDHC1 84
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#define VF610_CLK_DCU0_SEL 85
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#define VF610_CLK_DCU0_EN 86
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#define VF610_CLK_DCU0_DIV 87
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#define VF610_CLK_DCU0 88
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#define VF610_CLK_DCU1_SEL 89
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#define VF610_CLK_DCU1_EN 90
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#define VF610_CLK_DCU1_DIV 91
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#define VF610_CLK_DCU1 92
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#define VF610_CLK_ESAI_SEL 93
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#define VF610_CLK_ESAI_EN 94
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#define VF610_CLK_ESAI_DIV 95
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#define VF610_CLK_ESAI 96
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#define VF610_CLK_SAI0_SEL 97
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#define VF610_CLK_SAI0_EN 98
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#define VF610_CLK_SAI0_DIV 99
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#define VF610_CLK_SAI0 100
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#define VF610_CLK_SAI1_SEL 101
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#define VF610_CLK_SAI1_EN 102
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#define VF610_CLK_SAI1_DIV 103
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#define VF610_CLK_SAI1 104
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#define VF610_CLK_SAI2_SEL 105
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#define VF610_CLK_SAI2_EN 106
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#define VF610_CLK_SAI2_DIV 107
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#define VF610_CLK_SAI2 108
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#define VF610_CLK_SAI3_SEL 109
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#define VF610_CLK_SAI3_EN 110
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#define VF610_CLK_SAI3_DIV 111
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#define VF610_CLK_SAI3 112
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#define VF610_CLK_USBC0 113
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#define VF610_CLK_USBC1 114
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#define VF610_CLK_QSPI0_SEL 115
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#define VF610_CLK_QSPI0_EN 116
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#define VF610_CLK_QSPI0_X4_DIV 117
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#define VF610_CLK_QSPI0_X2_DIV 118
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#define VF610_CLK_QSPI0_X1_DIV 119
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#define VF610_CLK_QSPI1_SEL 120
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#define VF610_CLK_QSPI1_EN 121
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#define VF610_CLK_QSPI1_X4_DIV 122
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#define VF610_CLK_QSPI1_X2_DIV 123
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#define VF610_CLK_QSPI1_X1_DIV 124
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#define VF610_CLK_QSPI0 125
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#define VF610_CLK_QSPI1 126
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#define VF610_CLK_NFC_SEL 127
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#define VF610_CLK_NFC_EN 128
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#define VF610_CLK_NFC_PRE_DIV 129
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#define VF610_CLK_NFC_FRAC_DIV 130
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#define VF610_CLK_NFC_INV 131
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#define VF610_CLK_NFC 132
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#define VF610_CLK_VADC_SEL 133
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#define VF610_CLK_VADC_EN 134
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#define VF610_CLK_VADC_DIV 135
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#define VF610_CLK_VADC_DIV_HALF 136
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#define VF610_CLK_VADC 137
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#define VF610_CLK_ADC0 138
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#define VF610_CLK_ADC1 139
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#define VF610_CLK_DAC0 140
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#define VF610_CLK_DAC1 141
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#define VF610_CLK_FLEXCAN0 142
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#define VF610_CLK_FLEXCAN1 143
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#define VF610_CLK_ASRC 144
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#define VF610_CLK_GPU_SEL 145
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#define VF610_CLK_GPU_EN 146
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#define VF610_CLK_GPU2D 147
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#define VF610_CLK_ENET0 148
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#define VF610_CLK_ENET1 149
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#define VF610_CLK_DMAMUX0 150
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#define VF610_CLK_DMAMUX1 151
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#define VF610_CLK_DMAMUX2 152
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#define VF610_CLK_DMAMUX3 153
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#define VF610_CLK_FLEXCAN0_EN 154
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#define VF610_CLK_FLEXCAN1_EN 155
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#define VF610_CLK_PLL7_USB_HOST 156
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#define VF610_CLK_USBPHY0 157
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#define VF610_CLK_USBPHY1 158
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#define VF610_CLK_LVDS1_IN 159
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#define VF610_CLK_ANACLK1 160
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#define VF610_CLK_PLL1_BYPASS_SRC 161
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#define VF610_CLK_PLL2_BYPASS_SRC 162
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#define VF610_CLK_PLL3_BYPASS_SRC 163
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#define VF610_CLK_PLL4_BYPASS_SRC 164
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#define VF610_CLK_PLL5_BYPASS_SRC 165
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#define VF610_CLK_PLL6_BYPASS_SRC 166
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#define VF610_CLK_PLL7_BYPASS_SRC 167
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#define VF610_CLK_PLL1 168
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#define VF610_CLK_PLL2 169
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#define VF610_CLK_PLL3 170
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#define VF610_CLK_PLL4 171
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#define VF610_CLK_PLL5 172
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#define VF610_CLK_PLL6 173
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#define VF610_CLK_PLL7 174
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#define VF610_PLL1_BYPASS 175
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#define VF610_PLL2_BYPASS 176
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#define VF610_PLL3_BYPASS 177
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#define VF610_PLL4_BYPASS 178
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#define VF610_PLL5_BYPASS 179
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#define VF610_PLL6_BYPASS 180
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#define VF610_PLL7_BYPASS 181
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#define VF610_CLK_SNVS 182
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#define VF610_CLK_DAP 183
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#define VF610_CLK_OCOTP 184
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#define VF610_CLK_DDRMC 185
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#define VF610_CLK_WKPU 186
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#define VF610_CLK_TCON0 187
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#define VF610_CLK_TCON1 188
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#define VF610_CLK_CAAM 189
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#define VF610_CLK_CRC 190
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#define VF610_CLK_END 191
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#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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