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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
63 lines
2.3 KiB
C
63 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*/
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#ifndef IS43TR16512BL_H
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#define IS43TR16512BL_H
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/* DMC0 setup for the EV-21593-SOM and EV-SC594-SOM :
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* - uses a single 8GB IS43TR16512BL-125KBL DDR3 chip configured for
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* 800 MHz DCLK.
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* DMC0 setup for the EV-SC594-SOMS :
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* - uses a single 4GB IS43TR16256BL-093NBL DDR3 chip configured for
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* 800 MHz DCLK.
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*/
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#define DMC_DLLCALRDCNT 240
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#define DMC_DATACYC 12
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#define DMC_TRCD 11
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#define DMC_TWTR 6
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#define DMC_TRP 11
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#define DMC_TRAS 28
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#define DMC_TRC 39
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#define DMC_TMRD 4
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#define DMC_TREF 6240
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#define DMC_TRRD 6
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#define DMC_TFAW 32
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#define DMC_TRTP 6
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#define DMC_TWR 12
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#define DMC_TXP 5
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#define DMC_TCKE 4
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#define DMC_CL0 0
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#define DMC_CL123 7
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#define DMC_WRRECOV 6
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#define DMC_MR1_DLLEN 0
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#define DMC_MR1_DIC0 0
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#define DMC_MR1_RTT0 0
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#define DMC_MR1_AL 0
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#define DMC_MR1_DIC1 0
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#define DMC_MR1_RTT1 1
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#define DMC_MR1_WL 0
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#define DMC_MR1_RTT2 0
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#define DMC_MR1_TDQS 0
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#define DMC_MR1_QOFF 0
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#define DMC_WL 3
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#define DMC_RDTOWR 5
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#define DMC_CTL_AL_EN 1
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#if defined(MEM_ISSI_4Gb_DDR3_800MHZ)
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#define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE4G)
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#define DMC_TRFC 208ul
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#elif defined(MEM_ISSI_8Gb_DDR3_800MHZ)
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#define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE8G)
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#define DMC_TRFC 280ul
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#else
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#error "Need to select MEM_ISSI_4Gb_DDR3_800MHZ or MEM_ISSI_8Gb_DDR3_800MHZ"
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#endif
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#endif
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