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67ddd56251
DT node pic@40000 is defined explicitly in p2020-post.dtsi file and also transitionally via include file pq3-mpic.dtsi. Remove duplicate definition from p2020-post.dtsi. No change in final DTB file. Signed-off-by: Pali Rohár <pali@kernel.org>
198 lines
4.2 KiB
Plaintext
198 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P2020 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p2020-immr", "simple-bus";
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bus-frequency = <0x0>;
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p2020-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2 0 0>;
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};
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memory-controller@2000 {
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compatible = "fsl,p2020-memory-controller";
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reg = <0x2000 0x1000>;
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interrupts = <18 2 0 0>;
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};
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/include/ "pq3-i2c-0.dtsi"
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/include/ "pq3-i2c-1.dtsi"
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/include/ "pq3-duart-0.dtsi"
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espi0: spi@7000 {
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compatible = "fsl,mpc8536-espi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7000 0x1000>;
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interrupts = < 0x3b 0x02 0x00 0x00 >;
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fsl,espi-num-chipselects = <4>;
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};
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/include/ "pq3-dma-1.dtsi"
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/include/ "pq3-gpio-0.dtsi"
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p2020-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; /* 32 bytes */
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cache-size = <0x80000>; /* L2,512K */
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-dma-0.dtsi"
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usb@22000 {
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compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
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reg = <0x22000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <28 0x2 0 0>;
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phy_type = "ulpi";
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};
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/include/ "pq3-etsec1-0.dtsi"
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/include/ "pq3-etsec1-timer-0.dtsi"
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ptp_clock@24e00 {
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interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
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};
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/include/ "pq3-etsec1-1.dtsi"
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/include/ "pq3-etsec1-2.dtsi"
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esdhc: sdhc@2e000 {
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compatible = "fsl,p2020-esdhc", "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <72 0x2 0 0>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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/include/ "pq3-sec3.1-0.dtsi"
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/include/ "pq3-mpic.dtsi"
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/include/ "pq3-mpic-timer-B.dtsi"
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global-utilities@e0000 {
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compatible = "fsl,p2020-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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pmc: power@e0070 {
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compatible = "fsl,mpc8548-pmc";
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reg = <0xe0070 0x20>;
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};
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};
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/* PCIe controller base address 0x8000 */
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&pci2 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
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law_trgt_if = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <24 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <24 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
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>;
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};
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};
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/* PCIe controller base address 0x9000 */
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&pci1 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
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law_trgt_if = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <25 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <25 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
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>;
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};
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};
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/* PCIe controller base address 0xa000 */
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&pci0 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie";
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law_trgt_if = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <26 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <26 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
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>;
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};
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};
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&lbc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
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interrupts = <19 2 0 0>;
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};
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