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42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Yong Liang <yong.liang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
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/* TOPRGU resets */
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#define MT8192_TOPRGU_MM_SW_RST 1
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#define MT8192_TOPRGU_MFG_SW_RST 2
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#define MT8192_TOPRGU_VENC_SW_RST 3
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#define MT8192_TOPRGU_VDEC_SW_RST 4
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#define MT8192_TOPRGU_IMG_SW_RST 5
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#define MT8192_TOPRGU_MD_SW_RST 7
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#define MT8192_TOPRGU_CONN_SW_RST 9
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#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
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#define MT8192_TOPRGU_IPU0_SW_RST 14
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#define MT8192_TOPRGU_IPU1_SW_RST 15
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#define MT8192_TOPRGU_AUDIO_SW_RST 17
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#define MT8192_TOPRGU_CAMSYS_SW_RST 18
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#define MT8192_TOPRGU_MJC_SW_RST 19
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#define MT8192_TOPRGU_C2K_S2_SW_RST 20
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#define MT8192_TOPRGU_C2K_SW_RST 21
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#define MT8192_TOPRGU_PERI_SW_RST 22
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#define MT8192_TOPRGU_PERI_AO_SW_RST 23
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#define MT8192_TOPRGU_SW_RST_NUM 23
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/* MMSYS resets */
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#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
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/* INFRA resets */
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#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
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#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
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#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
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#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
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#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
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