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8a897c4f97
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* cm_t43.h
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*
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* Copyright (C) 2015 Compulab, Ltd.
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*/
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#ifndef __CONFIG_CM_T43_H
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#define __CONFIG_CM_T43_H
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#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
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#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
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#include <asm/arch/omap.h>
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/* Serial support */
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#define CFG_SYS_NS16550_CLK 48000000
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#define CFG_SYS_NS16550_COM1 0x44e09000
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/* NAND support */
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#define CFG_SYS_NAND_ECCSIZE 512
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#define CFG_SYS_NAND_ECCBYTES 14
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#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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/* Enabling L2 Cache */
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#define CFG_SYS_PL310_BASE 0x48242000
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/*
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* Since SPL did pll and ddr initialization for us,
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* we don't need to do it twice.
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*/
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#include <configs/ti_armv7_omap.h>
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK)
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#define CFG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80200000\0" \
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"fdtaddr=0x81200000\0" \
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"bootm_size=0x8000000\0" \
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"console=ttyO0,115200n8\0" \
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"fdtfile=am437x-sb-som-t43.dtb\0" \
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"kernel=zImage-cm-t43\0" \
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"bootscr=bootscr.img\0" \
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"emmcroot=/dev/mmcblk0p2 rw\0" \
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"emmcrootfstype=ext4 rootwait\0" \
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"emmcargs=setenv bootargs console=${console} " \
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"root=${emmcroot} " \
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"rootfstype=${emmcrootfstype}\0" \
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"loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"emmcboot=echo Booting from emmc ... && " \
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"run emmcargs && " \
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"load mmc 1 ${loadaddr} ${kernel} && " \
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"load mmc 1 ${fdtaddr} ${fdtfile} && " \
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"bootz ${loadaddr} - ${fdtaddr}\0"
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/* SPL defines. */
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/* EEPROM */
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#endif /* __CONFIG_CM_T43_H */
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