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c74b2108e3
Add support for the following DaVinci boards: - DV_EVM - SCHMOOGIE - SONATA Changes: - Split into separate board directories - Removed changes to MTD_DEBUG (or whatever it's called) - New CONFIG_CMD party line followed - Some cosmetic fixes, cleanup etc. - Patches against the latest U-Boot tree as of now. - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. Here is an excerpt from session log on SCHMOOGIE... U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com> Acked-by: Stefan Roese <sr@denx.de>
143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
/*
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* Intel LXT971/LXT972 PHY Driver for TI DaVinci
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* (TMS320DM644x) based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* --------------------------------------------------------
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <net.h>
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#include <lxt971a.h>
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#include <asm/arch/emac_defs.h>
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#ifdef CONFIG_DRIVER_TI_EMAC
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#ifdef CONFIG_CMD_NET
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int lxt972_is_phy_connected(int phy_addr)
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{
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u_int16_t id1, id2;
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if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1))
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return(0);
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if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2))
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return(0);
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if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
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return(1);
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return(0);
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}
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int lxt972_get_link_speed(int phy_addr)
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{
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u_int16_t stat1, tmp;
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volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
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if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
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return(0);
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if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
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return(0);
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if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
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return(0);
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tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
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dm644x_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
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/* Read back */
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if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
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return(0);
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/* Speed doesn't matter, there is no setting for it in EMAC... */
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if (stat1 & PHY_LXT971_STAT2_100BTX) {
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if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
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/* set DM644x EMAC for Full Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
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} else {
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/*set DM644x EMAC for Half Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
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}
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return(1);
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} else {
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if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
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/* set DM644x EMAC for Full Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
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} else {
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/*set DM644x EMAC for Half Duplex */
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emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
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}
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return(1);
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}
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return(0);
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}
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int lxt972_init_phy(int phy_addr)
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{
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int ret = 1;
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if (!lxt972_get_link_speed(phy_addr)) {
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/* Try another time */
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ret = lxt972_get_link_speed(phy_addr);
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}
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/* Disable PHY Interrupts */
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dm644x_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
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return(ret);
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}
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int lxt972_auto_negotiate(int phy_addr)
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{
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u_int16_t tmp;
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if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp))
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return(0);
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/* Restart Auto_negotiation */
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tmp |= PHY_COMMON_CTRL_RES_AUTO;
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dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp);
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/*check AutoNegotiate complete */
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udelay (10000);
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if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp))
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return(0);
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if (!(tmp & PHY_COMMON_STAT_AN_COMP))
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return(0);
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return (lxt972_get_link_speed(phy_addr));
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* CONFIG_DRIVER_ETHER */
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