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02032e8f14
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
126 lines
3.4 KiB
C
126 lines
3.4 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor.
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* Jeffrey Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*/
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#ifndef __MPC86xx_H__
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#define __MPC86xx_H__
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#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
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#define _START_OFFSET EXC_OFF_SYS_RESET
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/*
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* platform register addresses
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*/
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#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4)
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#define MCM_ABCR (CFG_CCSRBAR + 0x01000)
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#define MCM_DBCR (CFG_CCSRBAR + 0x01008)
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/*
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* l2cr values. Look in config_<BOARD>.h for the actual setup
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*/
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#define l2cr 1017
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#define L2CR_L2E 0x80000000 /* bit 0 - enable */
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#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
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#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
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#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
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#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
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#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
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#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
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#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
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/*
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* BAT settings. Look in config_<BOARD>.h for the actual setup
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*/
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#define BATU_BL_128K 0x00000000
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#define BATU_BL_256K 0x00000004
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#define BATU_BL_512K 0x0000000c
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#define BATU_BL_1M 0x0000001c
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#define BATU_BL_2M 0x0000003c
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#define BATU_BL_4M 0x0000007c
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#define BATU_BL_8M 0x000000fc
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#define BATU_BL_16M 0x000001fc
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#define BATU_BL_32M 0x000003fc
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#define BATU_BL_64M 0x000007fc
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#define BATU_BL_128M 0x00000ffc
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#define BATU_BL_256M 0x00001ffc
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#define BATU_BL_512M 0x00003ffc
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#define BATU_BL_1G 0x00007ffc
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#define BATU_BL_2G 0x0000fffc
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#define BATU_BL_4G 0x0001fffc
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#define BATU_VS 0x00000002
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#define BATU_VP 0x00000001
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#define BATU_INVALID 0x00000000
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#define BATL_WRITETHROUGH 0x00000040
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#define BATL_CACHEINHIBIT 0x00000020
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#define BATL_MEMCOHERENCE 0x00000010
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#define BATL_GUARDEDSTORAGE 0x00000008
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#define BATL_NO_ACCESS 0x00000000
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#define BATL_PP_MSK 0x00000003
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#define BATL_PP_00 0x00000000 /* No access */
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#define BATL_PP_01 0x00000001 /* Read-only */
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#define BATL_PP_10 0x00000002 /* Read-write */
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#define BATL_PP_11 0x00000003
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#define BATL_PP_NO_ACCESS BATL_PP_00
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#define BATL_PP_RO BATL_PP_01
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#define BATL_PP_RW BATL_PP_10
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#define HID0_XBSEN 0x00000100
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#define HID0_HIGH_BAT_EN 0x00800000
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#define HID0_XAEN 0x00020000
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned long freqProcessor;
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unsigned long freqSystemBus;
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} MPC86xx_SYS_INFO;
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#define l1icache_enable icache_enable
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void l2cache_enable(void);
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void l1dcache_enable(void);
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static __inline__ unsigned long get_hid0 (void)
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{
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unsigned long hid0;
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asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
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return hid0;
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}
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static __inline__ unsigned long get_hid1 (void)
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{
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unsigned long hid1;
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asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
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return hid1;
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}
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static __inline__ void set_hid0 (unsigned long hid0)
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{
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asm volatile("mtspr 1008, %0" : : "r" (hid0));
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}
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static __inline__ void set_hid1 (unsigned long hid1)
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{
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asm volatile("mtspr 1009, %0" : : "r" (hid1));
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}
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static __inline__ unsigned long get_l2cr (void)
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{
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unsigned long l2cr_val;
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asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
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return l2cr_val;
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}
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#endif /* _ASMLANGUAGE */
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#endif /* __MPC86xx_H__ */
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