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3b2979eefa
The definition of CONFIG_SPL_BOOTROM_SAVE is always a fixed CONFIG_SPL_STACK + 4, while CONFIG_SPL_STACK is not constant. This change will make it clear where the location is still, once CONFIG_SPL_STACK moves to Kconfig. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
80 lines
1.9 KiB
ArmAsm
80 lines
1.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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#include <config.h>
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#include <linux/linkage.h>
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/*
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* BootROM loads the header part of kwbimage into L2 cache. BIN header usually
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* contains U-Boot SPL, optionally it can also contain additional arguments.
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* The number of these arguments is in r0, pointer to the argument array in r1.
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* BootROM expects executable BIN header code to return to address stored in lr.
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* Other registers (r2 - r12) must be preserved. We save all registers to the
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* address of CONFIG_SPL_STACK + 4. BIN header arguments (passed via r0 and r1)
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* are currently not used by U-Boot SPL binary.
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*/
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ENTRY(save_boot_params)
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stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
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ldr r12, =(CONFIG_SPL_STACK + 4)
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str sp, [r12]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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ENTRY(return_to_bootrom)
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ldr r12, =(CONFIG_SPL_STACK + 4)
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ldr sp, [r12]
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ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
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mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
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bx lr /* @ return to bootrom */
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ENDPROC(return_to_bootrom)
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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