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660d5f0d49
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
25 lines
553 B
C
25 lines
553 B
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arcregs.h>
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#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */
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int timer_init(void)
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{
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write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
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/* Set max value for counter/timer */
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write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
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/* Set initial count value and restart counter/timer */
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write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return read_aux_reg(ARC_AUX_TIMER0_CNT);
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}
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